#define RTL931X_RMA_CTRL_1 (0x8804)
#define RTL931X_RMA_CTRL_2 (0x8808)
-/* Advanced SMI control for clause 45 PHYs */
-#define RTL930X_SMI_MAC_TYPE_CTRL (0xCA04)
-#define RTL930X_SMI_PORT24_27_ADDR_CTRL (0xCB90)
-#define RTL930X_SMI_PORT0_15_POLLING_SEL (0xCA08)
-#define RTL930X_SMI_PORT16_27_POLLING_SEL (0xCA0C)
-
-#define RTL930X_SMI_10GPHY_POLLING_REG0_CFG (0xCBB4)
-#define RTL930X_SMI_10GPHY_POLLING_REG9_CFG (0xCBB8)
-#define RTL930X_SMI_10GPHY_POLLING_REG10_CFG (0xCBBC)
-#define RTL930X_SMI_PRVTE_POLLING_CTRL (0xCA10)
-
/* Chip configuration registers of the RTL9310 */
#define RTL931X_MEM_ENCAP_INIT (0x4854)
#define RTL931X_MEM_MIB_INIT (0x7E18)
#define RTL931X_MEM_ALE_INIT_2 (0x82E4)
#define RTL931X_MDX_CTRL_RSVD (0x0fcc)
#define RTL931X_PS_SOC_CTRL (0x13f8)
-#define RTL931X_SMI_10GPHY_POLLING_SEL2 (0xCF8)
-#define RTL931X_SMI_10GPHY_POLLING_SEL3 (0xCFC)
-#define RTL931X_SMI_10GPHY_POLLING_SEL4 (0xD00)
/* shared CPU tag definitions for RTL930X/RTL931X */
#define RTL93XX_CPU_TAG1_FWD_MASK GENMASK(11, 8)