Add child node nand@0 and move NAND related property under it to align
modern nand-controller.yaml.
Fix below CHECK_DTBS warnings:
arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtb: nand-controller@
1806000 (fsl,imx6q-gpmi-nand): Unevaluated properties are not allowed ('nand-ecc-mode', 'nand-ecc-step-size', 'nand-ecc-strength', 'nand-on-flash-bbt' were unexpected)
from schema $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
Since 2019 year, commit
(
212e496935929 dt-bindings: mtd: Add YAML schemas for the generic NAND options)
NAND related property is preferred located under nand@<n> even though only
one NAND chip supported.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ };
};
&i2c3 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ };
};
&i2c1 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ };
};
&i2c1 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
status = "disabled";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ };
};
&i2c3 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ };
};
&i2c3 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
fsl,no-blockmark-swap;
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ };
};
&i2c1 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ };
};
&i2c1 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
status = "disabled";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ };
};
&i2c1 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
status = "disabled";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ };
};
&i2c1 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
fsl,no-blockmark-swap;
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ };
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
fsl,use-minimum-ecc;
- nand-on-flash-bbt;
- nand-ecc-mode = "hw";
- nand-ecc-strength = <8>;
- nand-ecc-step-size = <512>;
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ };
};
/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-ecc-mode = "hw";
- nand-ecc-strength = <0>;
- nand-ecc-step-size = <0>;
- nand-on-flash-bbt;
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <0>;
+ nand-ecc-step-size = <0>;
+ nand-on-flash-bbt;
+ };
};
&iomuxc {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
status = "disabled";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ };
};
&uart1 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ };
};
&snvs_poweroff {
/* NAND on such SKUs */
&gpmi {
fsl,use-minimum-ecc;
- nand-ecc-mode = "hw";
- nand-on-flash-bbt;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ };
};
/* On-module Power I2C */