Add missing conditional move patterns

From-SVN: r40966

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5bd0802858b993cc942d6ff1e42a1987cf0b8e34..ef4dfa751993921c8ab1f215bcdc74d11ca25cf7 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -7,6 +7,10 @@
 
        * final.c (cleanup_subreg_operands): Also clean up inside MEMs.
 
+       Mon Oct  4 02:31:20 1999  Mark Mitchell  <mark@codesourcery.com>
+       * mips.md: Define conditional move patterns for floating point
+       operands and DI mode conditions.
+
 2001-03-28  Bernd Schmidt  <bernds@redhat.com>
 
        * flow.c (propagate_block): When trying to delete a case vector, cope

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 81c5cd38e3811b918300456fe3d1748fc291b67f..cc1282c7386207c4501c7697f23d846b9e8f3e5d 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -10083,6 +10083,21 @@ move\\t%0,%z4\\n\\
   [(set_attr "type" "move")
    (set_attr "mode" "SF")])
 
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=f,f")
+       (if_then_else:SF
+        (match_operator 4 "equality_op"
+                        [(match_operand:DI 1 "se_register_operand" "d,d")
+                         (const_int 0)])
+        (match_operand:SF 2 "register_operand" "f,0")
+        (match_operand:SF 3 "register_operand" "0,f")))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT"
+  "@
+    mov%B4.s\\t%0,%2,%1
+    mov%b4.s\\t%0,%3,%1"
+  [(set_attr "type" "move")
+   (set_attr "mode" "SF")])
+
 (define_insn ""
   [(set (match_operand:SF 0 "register_operand" "=f,f")
        (if_then_else:SF
@@ -10114,6 +10129,21 @@ move\\t%0,%z4\\n\\
   [(set_attr "type" "move")
    (set_attr "mode" "DF")])
 
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=f,f")
+       (if_then_else:DF
+        (match_operator 4 "equality_op"
+                        [(match_operand:DI 1 "se_register_operand" "d,d")
+                         (const_int 0)])
+        (match_operand:DF 2 "register_operand" "f,0")
+        (match_operand:DF 3 "register_operand" "0,f")))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "@
+    mov%B4.d\\t%0,%2,%1
+    mov%b4.d\\t%0,%3,%1"
+  [(set_attr "type" "move")
+   (set_attr "mode" "DF")])
+
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f,f")
        (if_then_else:DF