drm: sun4i: de2/de3: add mixer version enum

The Allwinner DE2 and DE3 display engine mixers are currently identified
by a simple boolean flag. This will not scale to support additional DE
variants.

Convert the boolean flag to an enum.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Link: https://lore.kernel.org/r/20250528092431.28825-2-ryan@testtoast.com
Signed-off-by: Maxime Ripard <mripard@kernel.org>

diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
index 58480d8e4f7042d0593d686fb0a0116898d2fc4f..c100d29b1a898ff75aa7d5da60ff5b0e654a27e4 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
+++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
@@ -212,7 +212,7 @@ void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
 {
        u32 base;
 
-       if (mixer->cfg->is_de3) {
+       if (mixer->cfg->de_type == SUN8I_MIXER_DE3) {
                sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, layer,
                                                mode, encoding, range);
                return;
@@ -228,7 +228,7 @@ void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable)
 {
        u32 base;
 
-       if (mixer->cfg->is_de3) {
+       if (mixer->cfg->de_type == SUN8I_MIXER_DE3) {
                sun8i_de3_ccsc_enable(mixer->engine.regs, layer, enable);
                return;
        }

diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 8b41d33baa30968cf0836db060cbd78aea8605a7..f5368761aad94b1cd64625f7d7dffbcc6f3cca70 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -537,7 +537,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
        base = sun8i_blender_base(mixer);
 
        /* Reset registers and disable unused sub-engines */
-       if (mixer->cfg->is_de3) {
+       if (mixer->cfg->de_type == SUN8I_MIXER_DE3) {
                for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4)
                        regmap_write(mixer->engine.regs, i, 0);
 
@@ -628,6 +628,7 @@ static void sun8i_mixer_remove(struct platform_device *pdev)
 
 static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = {
        .ccsc           = CCSC_MIXER0_LAYOUT,
+       .de_type        = SUN8I_MIXER_DE2,
        .scaler_mask    = 0xf,
        .scanline_yuv   = 2048,
        .ui_num         = 3,
@@ -636,6 +637,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = {
 
 static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = {
        .ccsc           = CCSC_MIXER1_LAYOUT,
+       .de_type        = SUN8I_MIXER_DE2,
        .scaler_mask    = 0x3,
        .scanline_yuv   = 2048,
        .ui_num         = 1,
@@ -644,6 +646,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = {
 
 static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
        .ccsc           = CCSC_MIXER0_LAYOUT,
+       .de_type        = SUN8I_MIXER_DE2,
        .mod_rate       = 432000000,
        .scaler_mask    = 0xf,
        .scanline_yuv   = 2048,
@@ -653,6 +656,7 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
 
 static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
        .ccsc           = CCSC_MIXER0_LAYOUT,
+       .de_type        = SUN8I_MIXER_DE2,
        .mod_rate       = 297000000,
        .scaler_mask    = 0xf,
        .scanline_yuv   = 2048,
@@ -662,6 +666,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
 
 static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
        .ccsc           = CCSC_MIXER1_LAYOUT,
+       .de_type        = SUN8I_MIXER_DE2,
        .mod_rate       = 297000000,
        .scaler_mask    = 0x3,
        .scanline_yuv   = 2048,
@@ -670,6 +675,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
 };
 
 static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
+       .de_type = SUN8I_MIXER_DE2,
        .vi_num = 2,
        .ui_num = 1,
        .scaler_mask = 0x3,
@@ -680,6 +686,7 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
 
 static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = {
        .ccsc           = CCSC_D1_MIXER0_LAYOUT,
+       .de_type        = SUN8I_MIXER_DE2,
        .mod_rate       = 297000000,
        .scaler_mask    = 0x3,
        .scanline_yuv   = 2048,
@@ -689,6 +696,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = {
 
 static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = {
        .ccsc           = CCSC_MIXER1_LAYOUT,
+       .de_type        = SUN8I_MIXER_DE2,
        .mod_rate       = 297000000,
        .scaler_mask    = 0x1,
        .scanline_yuv   = 1024,
@@ -698,6 +706,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = {
 
 static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = {
        .ccsc           = CCSC_MIXER0_LAYOUT,
+       .de_type        = SUN8I_MIXER_DE2,
        .mod_rate       = 297000000,
        .scaler_mask    = 0xf,
        .scanline_yuv   = 4096,
@@ -707,6 +716,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = {
 
 static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
        .ccsc           = CCSC_MIXER1_LAYOUT,
+       .de_type        = SUN8I_MIXER_DE2,
        .mod_rate       = 297000000,
        .scaler_mask    = 0x3,
        .scanline_yuv   = 2048,
@@ -716,7 +726,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
 
 static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = {
        .ccsc           = CCSC_MIXER0_LAYOUT,
-       .is_de3         = true,
+       .de_type        = SUN8I_MIXER_DE3,
        .mod_rate       = 600000000,
        .scaler_mask    = 0xf,
        .scanline_yuv   = 4096,

diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index d7898c9c9cc0c86a8ded4444b260a83b3841db48..d34e7fb3143a37777a829dadb4e17e59a25ed050 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -151,6 +151,11 @@ enum {
        CCSC_D1_MIXER0_LAYOUT,
 };
 
+enum sun8i_mixer_type {
+       SUN8I_MIXER_DE2,
+       SUN8I_MIXER_DE3,
+};
+
 /**
  * struct sun8i_mixer_cfg - mixer HW configuration
  * @vi_num: number of VI channels
@@ -162,7 +167,7 @@ enum {
  * @ccsc: select set of CCSC base addresses from the enumeration above.
  * @mod_rate: module clock rate that needs to be set in order to have
  *     a functional block.
- * @is_de3: true, if this is next gen display engine 3.0, false otherwise.
+ * @de_type: sun8i_mixer_type enum representing the display engine generation.
  * @scaline_yuv: size of a scanline for VI scaler for YUV formats.
  */
 struct sun8i_mixer_cfg {
@@ -171,7 +176,7 @@ struct sun8i_mixer_cfg {
        int             scaler_mask;
        int             ccsc;
        unsigned long   mod_rate;
-       unsigned int    is_de3 : 1;
+       unsigned int    de_type;
        unsigned int    scanline_yuv;
 };
 
@@ -214,13 +219,13 @@ engine_to_sun8i_mixer(struct sunxi_engine *engine)
 static inline u32
 sun8i_blender_base(struct sun8i_mixer *mixer)
 {
-       return mixer->cfg->is_de3 ? DE3_BLD_BASE : DE2_BLD_BASE;
+       return mixer->cfg->de_type == SUN8I_MIXER_DE3 ? DE3_BLD_BASE : DE2_BLD_BASE;
 }
 
 static inline u32
 sun8i_channel_base(struct sun8i_mixer *mixer, int channel)
 {
-       if (mixer->cfg->is_de3)
+       if (mixer->cfg->de_type == SUN8I_MIXER_DE3)
                return DE3_CH_BASE + channel * DE3_CH_SIZE;
        else
                return DE2_CH_BASE + channel * DE2_CH_SIZE;

diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
index ae0806bccac7fef86b99fd572d75e1cedb61c9af..8b7a58e275171112428af5016c716633cf486fb2 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
@@ -93,7 +93,7 @@ static u32 sun8i_ui_scaler_base(struct sun8i_mixer *mixer, int channel)
 {
        int vi_num = mixer->cfg->vi_num;
 
-       if (mixer->cfg->is_de3)
+       if (mixer->cfg->de_type == SUN8I_MIXER_DE3)
                return DE3_VI_SCALER_UNIT_BASE +
                       DE3_VI_SCALER_UNIT_SIZE * vi_num +
                       DE3_UI_SCALER_UNIT_SIZE * (channel - vi_num);

diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
index 9c09d9c08496d6c39e20d6e2cf67f8436474e8bb..112f0a37cf4a797872d0d2e7a010ac36b6079a70 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
@@ -25,7 +25,7 @@ static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
 
        ch_base = sun8i_channel_base(mixer, channel);
 
-       if (mixer->cfg->is_de3) {
+       if (mixer->cfg->de_type >= SUN8I_MIXER_DE3) {
                mask = SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK |
                       SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_MASK;
                val = SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA
@@ -483,7 +483,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
        if (!layer)
                return ERR_PTR(-ENOMEM);
 
-       if (mixer->cfg->is_de3) {
+       if (mixer->cfg->de_type >= SUN8I_MIXER_DE3) {
                formats = sun8i_vi_layer_de3_formats;
                format_count = ARRAY_SIZE(sun8i_vi_layer_de3_formats);
        } else {
@@ -507,7 +507,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
 
        plane_cnt = mixer->cfg->ui_num + mixer->cfg->vi_num;
 
-       if (mixer->cfg->vi_num == 1 || mixer->cfg->is_de3) {
+       if (mixer->cfg->vi_num == 1 || mixer->cfg->de_type >= SUN8I_MIXER_DE3) {
                ret = drm_plane_create_alpha_property(&layer->plane);
                if (ret) {
                        dev_err(drm->dev, "Couldn't add alpha property\n");
@@ -524,7 +524,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
 
        supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) |
                              BIT(DRM_COLOR_YCBCR_BT709);
-       if (mixer->cfg->is_de3)
+       if (mixer->cfg->de_type >= SUN8I_MIXER_DE3)
                supported_encodings |= BIT(DRM_COLOR_YCBCR_BT2020);
 
        supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |

diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
index 7ba75011adf9fa3a8a95e4ace1b06144c16a5640..bd03607c8b7fa6b3560fca9c1ebad58304b26218 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
@@ -835,7 +835,7 @@ static const u32 bicubic4coefftab32[480] = {
 
 static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel)
 {
-       if (mixer->cfg->is_de3)
+       if (mixer->cfg->de_type == SUN8I_MIXER_DE3)
                return DE3_VI_SCALER_UNIT_BASE +
                       DE3_VI_SCALER_UNIT_SIZE * channel;
        else
@@ -956,7 +956,7 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
                cvphase = vphase;
        }
 
-       if (mixer->cfg->is_de3) {
+       if (mixer->cfg->de_type >= SUN8I_MIXER_DE3) {
                u32 val;
 
                if (format->hsub == 1 && format->vsub == 1)