riscv, bpf: make some atomic operations fully ordered

[ Upstream commit 20a759df3bba35bf5c3ddec0c02ad69b603b584c ]

The BPF atomic operations with the BPF_FETCH modifier along with
BPF_XCHG and BPF_CMPXCHG are fully ordered but the RISC-V JIT implements
all atomic operations except BPF_CMPXCHG with relaxed ordering.

Section 8.1 of the "The RISC-V Instruction Set Manual Volume I:
Unprivileged ISA" [1], titled, "Specifying Ordering of Atomic
Instructions" says:

| To provide more efficient support for release consistency [5], each
| atomic instruction has two bits, aq and rl, used to specify additional
| memory ordering constraints as viewed by other RISC-V harts.

and

| If only the aq bit is set, the atomic memory operation is treated as
| an acquire access.
| If only the rl bit is set, the atomic memory operation is treated as a
| release access.
|
| If both the aq and rl bits are set, the atomic memory operation is
| sequentially consistent.

Fix this by setting both aq and rl bits as 1 for operations with
BPF_FETCH and BPF_XCHG.

[1] https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf

Fixes: dd642ccb45ec ("riscv, bpf: Implement more atomic operations for RV64")
Signed-off-by: Puranjay Mohan <puranjay@kernel.org>
Reviewed-by: Pu Lehui <pulehui@huawei.com>
Link: https://lore.kernel.org/r/20240505201633.123115-1-puranjay@kernel.org
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
index 0bd747d1d00fc00a4e1ea117fb033bef8b3f54e5..29f031f68f480e67fd7438507b5793a603102f23 100644 (file)
--- a/arch/riscv/net/bpf_jit_comp64.c
+++ b/arch/riscv/net/bpf_jit_comp64.c
@@ -516,33 +516,33 @@ static void emit_atomic(u8 rd, u8 rs, s16 off, s32 imm, bool is64,
                break;
        /* src_reg = atomic_fetch_<op>(dst_reg + off16, src_reg) */
        case BPF_ADD | BPF_FETCH:
-               emit(is64 ? rv_amoadd_d(rs, rs, rd, 0, 0) :
-                    rv_amoadd_w(rs, rs, rd, 0, 0), ctx);
+               emit(is64 ? rv_amoadd_d(rs, rs, rd, 1, 1) :
+                    rv_amoadd_w(rs, rs, rd, 1, 1), ctx);
                if (!is64)
                        emit_zext_32(rs, ctx);
                break;
        case BPF_AND | BPF_FETCH:
-               emit(is64 ? rv_amoand_d(rs, rs, rd, 0, 0) :
-                    rv_amoand_w(rs, rs, rd, 0, 0), ctx);
+               emit(is64 ? rv_amoand_d(rs, rs, rd, 1, 1) :
+                    rv_amoand_w(rs, rs, rd, 1, 1), ctx);
                if (!is64)
                        emit_zext_32(rs, ctx);
                break;
        case BPF_OR | BPF_FETCH:
-               emit(is64 ? rv_amoor_d(rs, rs, rd, 0, 0) :
-                    rv_amoor_w(rs, rs, rd, 0, 0), ctx);
+               emit(is64 ? rv_amoor_d(rs, rs, rd, 1, 1) :
+                    rv_amoor_w(rs, rs, rd, 1, 1), ctx);
                if (!is64)
                        emit_zext_32(rs, ctx);
                break;
        case BPF_XOR | BPF_FETCH:
-               emit(is64 ? rv_amoxor_d(rs, rs, rd, 0, 0) :
-                    rv_amoxor_w(rs, rs, rd, 0, 0), ctx);
+               emit(is64 ? rv_amoxor_d(rs, rs, rd, 1, 1) :
+                    rv_amoxor_w(rs, rs, rd, 1, 1), ctx);
                if (!is64)
                        emit_zext_32(rs, ctx);
                break;
        /* src_reg = atomic_xchg(dst_reg + off16, src_reg); */
        case BPF_XCHG:
-               emit(is64 ? rv_amoswap_d(rs, rs, rd, 0, 0) :
-                    rv_amoswap_w(rs, rs, rd, 0, 0), ctx);
+               emit(is64 ? rv_amoswap_d(rs, rs, rd, 1, 1) :
+                    rv_amoswap_w(rs, rs, rd, 1, 1), ctx);
                if (!is64)
                        emit_zext_32(rs, ctx);
                break;