+2004-05-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ Backport from mainline
+
+ PR debug/15301
+ PR debug/15302
+ 2004-05-17 Jan Hubicka <jh@suse.cz>
+
+ * i386.c (construct_container): Do not produce BLKmode registers.
+ (classify_argument): Properly compute alignment of complex types.
2004-04-17 Eric Botcazou <ebotcazou@libertysurf.fr>
PR optimization/11841
mode_alignment = 128;
else if (mode == XCmode)
mode_alignment = 256;
+ if (COMPLEX_MODE_P (mode))
+ mode_alignment /= 2;
/* Misaligned fields are always returned in memory. */
if (bit_offset % mode_alignment)
return 0;
default:
abort ();
}
- if (n == 2 && class[0] == X86_64_SSE_CLASS && class[1] == X86_64_SSEUP_CLASS)
+ if (n == 2 && class[0] == X86_64_SSE_CLASS && class[1] == X86_64_SSEUP_CLASS
+ && mode != BLKmode)
return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
if (n == 2
&& class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS)
return gen_rtx_REG (mode, intreg[0]);
if (n == 4
&& class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS
- && class[2] == X86_64_X87_CLASS && class[3] == X86_64_X87UP_CLASS)
+ && class[2] == X86_64_X87_CLASS && class[3] == X86_64_X87UP_CLASS
+ && mode != BLKmode)
return gen_rtx_REG (TCmode, FIRST_STACK_REG);
/* Otherwise figure out the entries of the PARALLEL. */