clk: renesas: r9a09g056-cpg: Add clock and reset entries for OSTM instances

Introduce a new fixed divider .pllcln_div16 which is sourced from PLLCLN
and add PCLK module clocks gtm_0_pclk through gtm_7_pclk for OSTM0-7.
Add corresponding reset lines GTM_0_PRESETZ through GTM_7_PRESETZ to
control the OSTM instances.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513154635.273664-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c
index 5582041455c51a0d8a746d0466f9a2d72ba01348..c57583e7f6596ad91bf265a130a3b43633cb3169 100644 (file)
--- a/drivers/clk/renesas/r9a09g056-cpg.c
+++ b/drivers/clk/renesas/r9a09g056-cpg.c
@@ -34,6 +34,7 @@ enum clk_ids {
        CLK_PLLCM33_DIV16,
        CLK_PLLCLN_DIV2,
        CLK_PLLCLN_DIV8,
+       CLK_PLLCLN_DIV16,
        CLK_PLLDTY_ACPU,
        CLK_PLLDTY_ACPU_DIV4,
        CLK_PLLDTY_DIV8,
@@ -98,6 +99,7 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
 
        DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
        DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
+       DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
 
        DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
        DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
@@ -134,6 +136,22 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
 static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
        DEF_MOD_CRITICAL("gic_0_gicclk",        CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
                                                BUS_MSTOP(3, BIT(5))),
+       DEF_MOD("gtm_0_pclk",                   CLK_PLLCM33_DIV16, 4, 3, 2, 3,
+                                               BUS_MSTOP(5, BIT(10))),
+       DEF_MOD("gtm_1_pclk",                   CLK_PLLCM33_DIV16, 4, 4, 2, 4,
+                                               BUS_MSTOP(5, BIT(11))),
+       DEF_MOD("gtm_2_pclk",                   CLK_PLLCLN_DIV16, 4, 5, 2, 5,
+                                               BUS_MSTOP(2, BIT(13))),
+       DEF_MOD("gtm_3_pclk",                   CLK_PLLCLN_DIV16, 4, 6, 2, 6,
+                                               BUS_MSTOP(2, BIT(14))),
+       DEF_MOD("gtm_4_pclk",                   CLK_PLLCLN_DIV16, 4, 7, 2, 7,
+                                               BUS_MSTOP(11, BIT(13))),
+       DEF_MOD("gtm_5_pclk",                   CLK_PLLCLN_DIV16, 4, 8, 2, 8,
+                                               BUS_MSTOP(11, BIT(14))),
+       DEF_MOD("gtm_6_pclk",                   CLK_PLLCLN_DIV16, 4, 9, 2, 9,
+                                               BUS_MSTOP(11, BIT(15))),
+       DEF_MOD("gtm_7_pclk",                   CLK_PLLCLN_DIV16, 4, 10, 2, 10,
+                                               BUS_MSTOP(12, BIT(0))),
        DEF_MOD("scif_0_clk_pck",               CLK_PLLCM33_DIV16, 8, 15, 4, 15,
                                                BUS_MSTOP(3, BIT(14))),
        DEF_MOD("sdhi_0_imclk",                 CLK_PLLCLN_DIV8, 10, 3, 5, 3,
@@ -190,6 +208,14 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
        DEF_RST(3, 0, 1, 1),            /* SYS_0_PRESETN */
        DEF_RST(3, 8, 1, 9),            /* GIC_0_GICRESET_N */
        DEF_RST(3, 9, 1, 10),           /* GIC_0_DBG_GICRESET_N */
+       DEF_RST(6, 13, 2, 30),          /* GTM_0_PRESETZ */
+       DEF_RST(6, 14, 2, 31),          /* GTM_1_PRESETZ */
+       DEF_RST(6, 15, 3, 0),           /* GTM_2_PRESETZ */
+       DEF_RST(7, 0, 3, 1),            /* GTM_3_PRESETZ */
+       DEF_RST(7, 1, 3, 2),            /* GTM_4_PRESETZ */
+       DEF_RST(7, 2, 3, 3),            /* GTM_5_PRESETZ */
+       DEF_RST(7, 3, 3, 4),            /* GTM_6_PRESETZ */
+       DEF_RST(7, 4, 3, 5),            /* GTM_7_PRESETZ */
        DEF_RST(9, 5, 4, 6),            /* SCIF_0_RST_SYSTEM_N */
        DEF_RST(10, 7, 4, 24),          /* SDHI_0_IXRST */
        DEF_RST(10, 8, 4, 25),          /* SDHI_1_IXRST */