KVM: arm64: Fix various comments

Use tab instead of whitespaces, as well as 2 minor typo fixes.

Signed-off-by: Zenghui Yu (Huawei) <zenghui.yu@linux.dev>
Link: https://patch.msgid.link/20260128075208.23024-1-zenghui.yu@linux.dev
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 4c8b4274f669e33931ea1036b6dd9933a2542e69..fa01877a7ba11ed022ff2c3c3108b6eaa155add4 100644 (file)
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -201,7 +201,7 @@ struct kvm_s2_mmu {
         * host to parse the guest S2.
         * This either contains:
         * - the virtual VTTBR programmed by the guest hypervisor with
-         *   CnP cleared
+        *   CnP cleared
         * - The value 1 (VMID=0, BADDR=0, CnP=1) if invalid
         *
         * We also cache the full VTCR which gets used for TLB invalidation,

diff --git a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c
index f28c6cf4fe1be62dd9a5d3d3fd74c48668c996d4..b254d442e54e6522b6aea3a6ba2a1bdb774e22e9 100644 (file)
--- a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c
+++ b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c
@@ -205,7 +205,7 @@ void __vcpu_load_switch_sysregs(struct kvm_vcpu *vcpu)
 
        /*
         * When running a normal EL1 guest, we only load a new vcpu
-        * after a context switch, which imvolves a DSB, so all
+        * after a context switch, which involves a DSB, so all
         * speculative EL1&0 walks will have already completed.
         * If running NV, the vcpu may transition between vEL1 and
         * vEL2 without a context switch, so make sure we complete

diff --git a/arch/arm64/kvm/vgic/vgic-v3-nested.c b/arch/arm64/kvm/vgic/vgic-v3-nested.c
index 61b44f3f2bf140ffdd64fd2adf7c2c8eba31a278..a2ccef116483a09160d22c103b23f7bf1f39020a 100644 (file)
--- a/arch/arm64/kvm/vgic/vgic-v3-nested.c
+++ b/arch/arm64/kvm/vgic/vgic-v3-nested.c
@@ -57,7 +57,7 @@ static int lr_map_idx_to_shadow_idx(struct shadow_if *shadow_if, int idx)
  * as the L1 guest is in charge of provisioning the interrupts via its own
  * view of the ICH_LR*_EL2 registers, which conveniently live in the VNCR
  * page.  This means that the flow described above does work (there is no
- * state to rebuild in the L0 hypervisor), and that most things happed on L2
+ * state to rebuild in the L0 hypervisor), and that most things happen on L2
  * load/put:
  *
  * - on L2 load: move the in-memory L1 vGIC configuration into a shadow,