{NULL, NULL, ARM_ARCH_NONE, NULL}
};
+struct arm_ext_table
+{
+ const char * name;
+ size_t name_len;
+ const arm_feature_set merge;
+ const arm_feature_set clear;
+};
+
struct arm_cpu_option_table
{
const char * name;
/* The canonical name of the CPU, or NULL to use NAME converted to upper
case. */
const char * canonical_name;
+ const struct arm_ext_table * ext_table;
+};
+
+/* Used to add support for +E and +noE extension. */
+#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
+/* Used to add support for a +E extension. */
+#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
+/* Used to add support for a +noE extension. */
+#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
+
+#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
+ ~0 & ~FPU_ENDIAN_PURE)
+#define ALL_FP_MVE_FP ARM_FEATURE (0, (ARM_EXT2_FP16_INST \
+ | ARM_EXT2_FP16_FML \
+ | ARM_EXT2_MVE_FP), \
+ ~0 & ~FPU_ENDIAN_PURE)
+#define ALL_SIMD ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA \
+ | FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA \
+ | FPU_NEON_EXT_DOTPROD)
+
+#define CDE_EXTENSIONS \
+ ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
+ ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
+ ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
+ ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
+ ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
+ ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
+ ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
+ ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
+
+/* -mcpu extensions. */
+static const struct arm_ext_table cortex_a5_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ ARM_REMOVE ("simd", ALL_SIMD),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a7_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ ARM_REMOVE ("simd", ALL_SIMD),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a8_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a9_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ ARM_REMOVE ("simd", ALL_SIMD),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a12_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a15_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a17_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r5_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+ | FPU_VFP_EXT_ARMV8)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r7_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+ | FPU_VFP_EXT_ARMV8)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r8_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+ | FPU_VFP_EXT_ARMV8)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m4_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m7_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+ | FPU_VFP_EXT_ARMV8)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a32_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a35_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a53_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a57_ext_table[] =
+{
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a72_ext_table[] =
+{
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a73_ext_table[] =
+{
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table exynos_m1_ext_table[] =
+{
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r52_ext_table[] =
+{
+ ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_D32 | FPU_VFP_EXT_ARMV8
+ | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA
+ | FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA
+ | FPU_NEON_EXT_DOTPROD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r52plus_ext_table[] =
+{
+ ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_D32 | FPU_VFP_EXT_ARMV8
+ | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA
+ | FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA
+ | FPU_NEON_EXT_DOTPROD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m33_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ ARM_REMOVE ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m35p_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ ARM_REMOVE ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m52_ext_table[] =
+{
+ ARM_REMOVE ("pacbti", ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI)),
+ ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
+ ARM_REMOVE ("mve", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+ ARM_REMOVE ("fp", ALL_FP_MVE_FP),
+ ARM_REMOVE ("dsp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+ CDE_EXTENSIONS,
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m55_ext_table[] =
+{
+ ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
+ ARM_REMOVE ("mve", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+ ARM_REMOVE ("fp", ALL_FP_MVE_FP),
+ ARM_REMOVE ("dsp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+ CDE_EXTENSIONS,
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m85_ext_table[] =
+{
+ ARM_REMOVE ("pacbti", ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI)),
+ ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
+ ARM_REMOVE ("mve", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+ ARM_REMOVE ("fp", ALL_FP_MVE_FP),
+ ARM_REMOVE ("dsp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a55_ext_table[] =
+{
+ ARM_REMOVE ("fp", ALL_FP),
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a75_ext_table[] =
+{
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a76_ext_table[] =
+{
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a76ae_ext_table[] =
+{
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a77_ext_table[] =
+{
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a78_ext_table[] =
+{
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a78ae_ext_table[] =
+{
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a78c_ext_table[] =
+{
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_x1_ext_table[] =
+{
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_x1c_ext_table[] =
+{
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table neoverse_n1_ext_table[] =
+{
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table neoverse_v1_ext_table[] =
+{
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a710_ext_table[] =
+{
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table neoverse_n2_ext_table[] =
+{
+ ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+ | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
};
/* This list should, at a minimum, contain all the cpu names
recognized by GCC. */
-#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
+#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN, NULL }
+#define ARM_CPU_OPT2(N, CN, V, E, DF, ext) \
+ { N, sizeof (N) - 1, V, E, DF, CN, ext##_ext_table }
static const struct arm_cpu_option_table arm_cpus[] =
{
ARM_CPU_OPT ("arm1176jzf-s", NULL, ARM_ARCH_V6KZ,
ARM_ARCH_NONE,
FPU_ARCH_VFP_V2),
- ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A,
- ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
- FPU_ARCH_SOFTVFP),
- ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE,
- ARM_ARCH_NONE,
- FPU_ARCH_NEON_VFP_V4),
- ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A,
- ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
- ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
- ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A,
- ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
- ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
- ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE,
- ARM_ARCH_NONE,
- FPU_ARCH_NEON_VFP_V4),
- ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE,
- ARM_ARCH_NONE,
- FPU_ARCH_NEON_VFP_V4),
- ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE,
- ARM_ARCH_NONE,
- FPU_ARCH_NEON_VFP_V4),
- ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
- FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
- ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
- FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
- ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
- FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
- ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
- ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
- FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
- ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
- FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
- ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
- FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
- ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
- ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
- ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
- ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
- ARM_CPU_OPT ("cortex-a78", "Cortex-A78", ARM_ARCH_V8_2A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
- FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
- ARM_CPU_OPT ("cortex-a78ae", "Cortex-A78AE", ARM_ARCH_V8_2A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
- FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
- ARM_CPU_OPT ("cortex-a78c", "Cortex-A78C", ARM_ARCH_V8_2A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
- FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
- ARM_CPU_OPT ("cortex-a710", "Cortex-A710", ARM_ARCH_V9A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
- | ARM_EXT2_BF16
- | ARM_EXT2_I8MM),
- FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
- ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
+ ARM_CPU_OPT2 ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A,
+ ARM_FEATURE ((ARM_EXT_MP | ARM_EXT_SEC),
+ ARM_EXT2_FP16_INST,
+ (FPU_VFP_V4 | FPU_NEON_EXT_V1
+ | FPU_NEON_EXT_FMA)),
+ FPU_ARCH_NEON_VFP_V4,
+ cortex_a5),
+ ARM_CPU_OPT2 ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE,
+ ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1
+ | FPU_NEON_EXT_FMA),
+ FPU_ARCH_NEON_VFP_V4,
+ cortex_a7),
+ ARM_CPU_OPT2 ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A,
+ ARM_FEATURE_LOW (ARM_EXT_SEC, FPU_VFP_V3 | FPU_NEON_EXT_V1),
+ ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1),
+ cortex_a8),
+ ARM_CPU_OPT2 ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A,
+ ARM_FEATURE ((ARM_EXT_MP | ARM_EXT_SEC),
+ ARM_EXT2_FP16_INST,
+ (FPU_VFP_V4 | FPU_NEON_EXT_V1
+ | FPU_NEON_EXT_FMA)),
+ FPU_ARCH_NEON_VFP_V4,
+ cortex_a9),
+ ARM_CPU_OPT2 ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE,
+ ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1
+ | FPU_NEON_EXT_FMA),
+ FPU_ARCH_NEON_VFP_V4,
+ cortex_a12),
+ ARM_CPU_OPT2 ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE,
+ ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1
+ | FPU_NEON_EXT_FMA),
+ FPU_ARCH_NEON_VFP_V4,
+ cortex_a15),
+ ARM_CPU_OPT2 ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE,
+ ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1
+ | FPU_NEON_EXT_FMA),
+ FPU_ARCH_NEON_VFP_V4,
+ cortex_a17),
+ ARM_CPU_OPT2 ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A,
+ ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+ FPU_ARCH_NEON_VFP_ARMV8,
+ cortex_a32),
+ ARM_CPU_OPT2 ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A,
+ ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+ FPU_ARCH_NEON_VFP_ARMV8,
+ cortex_a35),
+ ARM_CPU_OPT2 ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A,
+ ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+ FPU_ARCH_NEON_VFP_ARMV8,
+ cortex_a53),
+ ARM_CPU_OPT2 ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A,
+ FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+ FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+ cortex_a55),
+ ARM_CPU_OPT2 ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A,
+ ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+ FPU_ARCH_NEON_VFP_ARMV8,
+ cortex_a57),
+ ARM_CPU_OPT2 ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A,
+ ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+ FPU_ARCH_NEON_VFP_ARMV8,
+ cortex_a72),
+ ARM_CPU_OPT2 ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A,
+ ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+ FPU_ARCH_NEON_VFP_ARMV8,
+ cortex_a73),
+ ARM_CPU_OPT2 ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A,
+ FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+ FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+ cortex_a75),
+ ARM_CPU_OPT2 ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A,
+ FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+ FPU_ARCH_VFP_V5_SP_D16,
+ cortex_a76),
+ ARM_CPU_OPT2 ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A,
+ FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+ FPU_ARCH_VFP_V5_SP_D16,
+ cortex_a76ae),
+ ARM_CPU_OPT2 ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A,
+ FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+ FPU_ARCH_VFP_V5_SP_D16,
+ cortex_a77),
+ ARM_CPU_OPT2 ("cortex-a78", "Cortex-A78", ARM_ARCH_V8_2A,
+ FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+ FPU_ARCH_VFP_V5_SP_D16,
+ cortex_a78),
+ ARM_CPU_OPT2 ("cortex-a78ae", "Cortex-A78AE", ARM_ARCH_V8_2A,
+ FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+ FPU_ARCH_VFP_V5_SP_D16,
+ cortex_a78ae),
+ ARM_CPU_OPT2 ("cortex-a78c", "Cortex-A78C", ARM_ARCH_V8_2A,
+ FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+ FPU_ARCH_VFP_V5_SP_D16,
+ cortex_a78c),
ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R,
ARM_ARCH_NONE,
FPU_ARCH_SOFTVFP),
ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R,
- ARM_ARCH_NONE,
- FPU_ARCH_VFP_V3D16),
- ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R,
- ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
- FPU_ARCH_SOFTVFP),
- ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R,
- ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
- FPU_ARCH_VFP_V3D16),
- ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R,
- ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
+ FPU_ARCH_VFP_V3D16,
FPU_ARCH_VFP_V3D16),
- ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
- FPU_ARCH_NEON_VFP_ARMV8),
- ARM_CPU_OPT ("cortex-r52plus", "Cortex-R52+", ARM_ARCH_V8R,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
- FPU_ARCH_NEON_VFP_ARMV8),
- ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN,
- ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
- FPU_ARCH_SOFTVFP),
- ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN,
- ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
- FPU_ARCH_SOFTVFP),
+ ARM_CPU_OPT2 ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R,
+ ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3),
+ FPU_ARCH_VFP_V3,
+ cortex_r5),
+ ARM_CPU_OPT2 ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R,
+ ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16),
+ FPU_ARCH_VFP_V3D16_FP16,
+ cortex_r7),
+ ARM_CPU_OPT2 ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R,
+ ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16),
+ FPU_ARCH_VFP_V3D16_FP16,
+ cortex_r8),
+ ARM_CPU_OPT2 ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R,
+ ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+ FPU_ARCH_NEON_VFP_ARMV8,
+ cortex_r52),
+ ARM_CPU_OPT2 ("cortex-r52plus", "Cortex-R52+", ARM_ARCH_V8R,
+ ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+ FPU_ARCH_NEON_VFP_ARMV8,
+ cortex_r52plus),
+ ARM_CPU_OPT2 ("cortex-m85", "Cortex-M85", ARM_ARCH_V8_1M_MAIN,
+ ARM_FEATURE_ALL(ARM_AEXT_V8M_MAIN_DSP,
+ (ARM_EXT2_FP16_INST | ARM_EXT2_MVE
+ | ARM_EXT2_MVE_FP),
+ ARM_EXT3_PACBTI,
+ (FPU_VFP_V5D16 | FPU_VFP_EXT_FP16
+ | FPU_VFP_EXT_FMA)),
+ FPU_ARCH_SOFTVFP,
+ cortex_m85),
+ ARM_CPU_OPT2 ("cortex-m55", "Cortex-M55", ARM_ARCH_V8_1M_MAIN,
+ ARM_FEATURE_ALL(ARM_AEXT_V8M_MAIN_DSP,
+ (ARM_EXT2_FP16_INST | ARM_EXT2_MVE
+ | ARM_EXT2_MVE_FP),
+ 0,
+ (FPU_VFP_V5D16 | FPU_VFP_EXT_FP16
+ | FPU_VFP_EXT_FMA)),
+ FPU_ARCH_SOFTVFP,
+ cortex_m55),
+ ARM_CPU_OPT2 ("cortex-m52", "Cortex-M52", ARM_ARCH_V8_1M_MAIN,
+ ARM_FEATURE_ALL (ARM_AEXT_V8M_MAIN_DSP,
+ (ARM_EXT2_FP16_INST | ARM_EXT2_MVE
+ | ARM_EXT2_MVE_FP),
+ ARM_EXT3_PACBTI,
+ (FPU_VFP_V5D16 | FPU_VFP_EXT_FP16
+ | FPU_VFP_EXT_FMA)),
+ FPU_ARCH_SOFTVFP,
+ cortex_m52),
+ ARM_CPU_OPT2 ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN,
+ ARM_FEATURE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP, FPU_VFP_V4D16),
+ FPU_ARCH_VFP_V3D16,
+ cortex_m35p),
+ ARM_CPU_OPT2 ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN,
+ ARM_FEATURE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP, FPU_VFP_V4D16),
+ FPU_ARCH_VFP_V3D16, cortex_m33),
ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE,
ARM_ARCH_NONE,
FPU_ARCH_SOFTVFP),
- ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM,
- ARM_ARCH_NONE,
- FPU_ARCH_SOFTVFP),
- ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM,
- ARM_ARCH_NONE,
- FPU_ARCH_SOFTVFP),
+ ARM_CPU_OPT2 ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM,
+ ARM_FEATURE_COPROC (FPU_VFP_V5D16),
+ FPU_ARCH_VFP_V5D16,
+ cortex_m7),
+ ARM_CPU_OPT2 ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM,
+ ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16),
+ FPU_ARCH_VFP_V4_SP_D16,
+ cortex_m4),
ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M,
ARM_ARCH_NONE,
FPU_ARCH_SOFTVFP),
ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM,
ARM_ARCH_NONE,
FPU_ARCH_SOFTVFP),
- ARM_CPU_OPT ("cortex-x1", "Cortex-X1", ARM_ARCH_V8_2A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
- FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
- ARM_CPU_OPT ("cortex-x1c", "Cortex-X1C", ARM_ARCH_V8_2A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
- FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
- ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
- FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
- ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
- ARM_CPU_OPT ("neoverse-n2", "Neoverse N2", ARM_ARCH_V8_5A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
- | ARM_EXT2_BF16
- | ARM_EXT2_I8MM),
- FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4),
- ARM_CPU_OPT ("neoverse-v1", "Neoverse V1", ARM_ARCH_V8_4A,
- ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
- | ARM_EXT2_BF16
- | ARM_EXT2_I8MM),
- FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4),
+ ARM_CPU_OPT2 ("cortex-x1", "Cortex-X1", ARM_ARCH_V8_2A,
+ FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+ FPU_ARCH_VFP_V5_SP_D16,
+ cortex_x1),
+ ARM_CPU_OPT2 ("cortex-x1c", "Cortex-X1C", ARM_ARCH_V8_2A,
+ FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+ FPU_ARCH_VFP_V5_SP_D16,
+ cortex_x1c),
+ ARM_CPU_OPT2 ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A,
+ ARM_FEATURE (0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+ FPU_ARCH_NEON_VFP_ARMV8,
+ exynos_m1),
+ ARM_CPU_OPT2 ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A,
+ FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+ FPU_ARCH_VFP_V5_SP_D16,
+ neoverse_n1),
+ ARM_CPU_OPT2 ("ares", "Ares", ARM_ARCH_V8_2A,
+ FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+ FPU_ARCH_VFP_V5_SP_D16,
+ neoverse_n1),
+ ARM_CPU_OPT2 ("neoverse-n2", "Neoverse N2", ARM_ARCH_V9A,
+ ARM_FEATURE(0,
+ (ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML
+ | ARM_EXT2_BF16 | ARM_EXT2_I8MM),
+ (FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8
+ | FPU_NEON_EXT_DOTPROD | FPU_NEON_EXT_RDMA)),
+ FPU_ARCH_VFP_V5_SP_D16,
+ neoverse_n2),
+ ARM_CPU_OPT2 ("cortex-a710", "Cortex-A710", ARM_ARCH_V9A,
+ ARM_FEATURE(0,
+ (ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML
+ | ARM_EXT2_BF16 | ARM_EXT2_I8MM),
+ (FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8
+ | FPU_NEON_EXT_DOTPROD | FPU_NEON_EXT_RDMA)),
+ FPU_ARCH_VFP_V5_SP_D16,
+ cortex_a710),
+ ARM_CPU_OPT2 ("neoverse-v1", "Neoverse V1", ARM_ARCH_V8_4A,
+ ARM_FEATURE(0,
+ (ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML
+ | ARM_EXT2_BF16 | ARM_EXT2_I8MM),
+ (FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8
+ | FPU_NEON_EXT_DOTPROD)),
+ FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+ neoverse_v1),
/* ??? XSCALE is really an architecture. */
ARM_CPU_OPT ("xscale", NULL, ARM_ARCH_XSCALE,
ARM_ARCH_NONE,
/* Marvell processors. */
ARM_CPU_OPT ("marvell-pj4", NULL, ARM_ARCH_V7A,
- ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
- FPU_ARCH_VFP_V3D16),
+ ARM_FEATURE (ARM_EXT_MP | ARM_EXT_SEC, 0, FPU_VFP_V3),
+ FPU_ARCH_VFP_V3),
ARM_CPU_OPT ("marvell-whitney", NULL, ARM_ARCH_V7A,
ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
FPU_ARCH_NEON_VFP_V4),
/* APM X-Gene family. */
ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A,
- ARM_ARCH_NONE,
+ ARM_FEATURE (0, 0, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A,
ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
- { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
+ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL, NULL }
};
#undef ARM_CPU_OPT
-
-struct arm_ext_table
-{
- const char * name;
- size_t name_len;
- const arm_feature_set merge;
- const arm_feature_set clear;
-};
+#undef ARM_CPU_OPT2
struct arm_arch_option_table
{
const struct arm_ext_table * ext_table;
};
-/* Used to add support for +E and +noE extension. */
-#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
-/* Used to add support for a +E extension. */
-#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
-/* Used to add support for a +noE extension. */
-#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
-
-#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
- ~0 & ~FPU_ENDIAN_PURE)
-
static const struct arm_ext_table armv5te_ext_table[] =
{
ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
#define armv94a_ext_table armv93a_ext_table
#define armv95a_ext_table armv94a_ext_table
-#define CDE_EXTENSIONS \
- ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
- ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
- ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
- ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
- ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
- ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
- ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
- ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
-
static const struct arm_ext_table armv8m_main_ext_table[] =
{
ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP),
}
if (ext != NULL)
- return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
+ return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, opt->ext_table);
return true;
}
Tag_CPU_arch_profile: Application
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv3
+ Tag_Advanced_SIMD_arch: NEONv1
Tag_Virtualization_use: TrustZone
--- /dev/null
+.syntax unified
+.thumb
+
+@ feat FP16
+vdot.bf16 q0, q1, q2
--- /dev/null
+.syntax unified
+
+@ feat CRC
+crc32w r0, r0, r1
--- /dev/null
+.syntax unified
+
+@ feat DOTPROD
+vudot.u8 q0, q1, q2
--- /dev/null
+.syntax unified
+
+@ feat DSP
+smlad r0, r1, r2, r3
--- /dev/null
+.syntax unified
+
+@ feat FP (VFP-v3)
+vmla.f32 s0, s1, s2
--- /dev/null
+.syntax unified
+
+@ feat FP (VFP-v5)
+vfma.f32 s0, s1, s2
--- /dev/null
+.syntax unified
+
+@ feat FP.DP
+vadd.f64 d0, d1, d2
--- /dev/null
+.syntax unified
+
+@ feat FP
+vadd.f32 s0, s1, s2
--- /dev/null
+.syntax unified
+
+@ feat FP16
+vadd.f16 q0, q1, q2
--- /dev/null
+.syntax unified
+
+@ feat I8MM
+vusmmla.s8 q6, q7, q8
--- /dev/null
+.syntax unified
+
+sdiv r0, r1, r2
--- /dev/null
+.syntax unified
+
+@ feat MP
+ldrex r0, [r1]
--- /dev/null
+.syntax unified
+.thumb
+
+@ MVE.FP
+vmul.f32 q0, q1, q2
--- /dev/null
+.syntax unified
+
+@ feat NEON-FP16
+vadd.f16 q0, q1, q2
--- /dev/null
+.syntax unified
+
+@ PACBTI
+pac r12, lr, sp
--- /dev/null
+.syntax unified
+
+@ feat SEC
+smc #0
--- /dev/null
+.syntax unified
+.text
+
+@ feat SIMD
+vadd.i32 q0, q1, q2
--- /dev/null
+.syntax unified
+
+@ feat VFP3-D16-FP16
+vcvtt.f16.f32 s0, s1
--- /dev/null
+#name: Cortex-A12 Attributes
+#as: -mcpu=cortex-a12+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A12"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_MPextension_use: Allowed
+ Tag_DIV_use: Allowed in v7-A with integer division extension
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A12 feat-simd
+#as: -mcpu=cortex-a12
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A12"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv4
+ Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+ Tag_MPextension_use: Allowed
+ Tag_DIV_use: Allowed in v7-A with integer division extension
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A15 Attributes
+#as: -mcpu=cortex-a15+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A15"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_MPextension_use: Allowed
+ Tag_DIV_use: Allowed in v7-A with integer division extension
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A15 feat-simd
+#as: -mcpu=cortex-a15
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A15"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv4
+ Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+ Tag_MPextension_use: Allowed
+ Tag_DIV_use: Allowed in v7-A with integer division extension
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A17 Attributes
+#as: -mcpu=cortex-a17+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A17"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_MPextension_use: Allowed
+ Tag_DIV_use: Allowed in v7-A with integer division extension
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A17 feat-simd
+#as: -mcpu=cortex-a17
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A17"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv4
+ Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+ Tag_MPextension_use: Allowed
+ Tag_DIV_use: Allowed in v7-A with integer division extension
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A32 Attributes
+#as: -mcpu=cortex-a32+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A32"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A32 Attributes 1
+#as: -mcpu=cortex-a32+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A32"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A32 feat-crc
+#as: -mcpu=cortex-a32
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A32"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A32 feat-simd
+#as: -mcpu=cortex-a32
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A32"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A35 Attributes
+#as: -mcpu=cortex-a35+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A35"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A35 Attributes 1
+#as: -mcpu=cortex-a35+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A35"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A35 feat-crc
+#as: -mcpu=cortex-a35
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A35"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A35 feat-simd
+#as: -mcpu=cortex-a35
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A35"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A5 Attributes
+#as: -mcpu=cortex-a5+nofp+nosimd
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A5"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone
--- /dev/null
+#name: Cortex-A5 feat-mp
+#as: -mcpu=cortex-a5
+#source: feat-mp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A5"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv4
+ Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone
--- /dev/null
+#name: Cortex-A5 feat-neon-fp16
+#as: -mcpu=cortex-a5
+#source: feat-neon-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A5"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv4
+ Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone
--- /dev/null
+#name: Cortex-A5 feat-sec
+#as: -mcpu=cortex-a5
+#source: feat-sec.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A5"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv4
+ Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone
--- /dev/null
+#name: Cortex-A53 Attributes
+#as: -mcpu=cortex-a53+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A53"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A53 Attributes 1
+#as: -mcpu=cortex-a53+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A53"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A53 feat-crc
+#as: -mcpu=cortex-a53
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A53"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A53 feat-simd
+#as: -mcpu=cortex-a53
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A53"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A55 Attributes
+#as: -mcpu=cortex-a55+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A55"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A55 Attributes 1
+#as: -mcpu=cortex-a55+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A55"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A55 feat-dotprod
+#as: -mcpu=cortex-a55
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A55"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A55 feat-fp16
+#as: -mcpu=cortex-a55
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A55"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A57 Attributes
+#as: -mcpu=cortex-a57+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A57"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A57 feat-crc
+#as: -mcpu=cortex-a57
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A57"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A57 feat-simd
+#as: -mcpu=cortex-a57
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A57"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A7 Attributes
+#as: -mcpu=cortex-a7+nofp+nosimd
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A7"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_MPextension_use: Allowed
+ Tag_DIV_use: Allowed in v7-A with integer division extension
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A7 feat-simd
+#as: -mcpu=cortex-a7
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A7"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv4
+ Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+ Tag_MPextension_use: Allowed
+ Tag_DIV_use: Allowed in v7-A with integer division extension
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A710 Attributes
+#as: -mcpu=cortex-a710+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A710"
+ Tag_CPU_arch: v9
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A710 feat-bf16
+#as: -mcpu=cortex-a710
+#source: feat-bf16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A710"
+ Tag_CPU_arch: v9
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A710 feat-fp16
+#as: -mcpu=cortex-a710
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A710"
+ Tag_CPU_arch: v9
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A710 feat-i8mm
+#as: -mcpu=cortex-a710
+#source: feat-i8mm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A710"
+ Tag_CPU_arch: v9
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A72 Attributes
+#as: -mcpu=cortex-a72+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A72"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A72 feat-crc
+#as: -mcpu=cortex-a72
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A72"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A72 feat-simd
+#as: -mcpu=cortex-a72
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A72"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A73 Attributes
+#as: -mcpu=cortex-a73+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A73"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A73 feat-crc
+#as: -mcpu=cortex-a73
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A73"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A73 feat-simd
+#as: -mcpu=cortex-a73
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A73"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A75 Attributes
+#as: -mcpu=cortex-a75+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A75"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A75 feat-dotprod
+#as: -mcpu=cortex-a75
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A75"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A75 feat-fp16
+#as: -mcpu=cortex-a75
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A75"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A76 Attributes
+#as: -mcpu=cortex-a76+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A76"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A76 feat-dotprod
+#as: -mcpu=cortex-a76
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A76"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A76 feat-fp16
+#as: -mcpu=cortex-a76
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A76"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A76AE Attributes
+#as: -mcpu=cortex-a76ae+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A76AE"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A76AE feat-dotprod
+#as: -mcpu=cortex-a76ae
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A76AE"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A76AE feat-fp16
+#as: -mcpu=cortex-a76ae
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A76AE"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A77 Attributes
+#as: -mcpu=cortex-a77+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A77"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A77 feat-dotprod
+#as: -mcpu=cortex-a77
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A77"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A77 feat-fp16
+#as: -mcpu=cortex-a77
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A77"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A78 Attributes
+#as: -mcpu=cortex-a78+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A78"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A78 feat-dotprod
+#as: -mcpu=cortex-a78
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A78"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A78 feat-fp16
+#as: -mcpu=cortex-a78
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A78"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A78AE Attributes
+#as: -mcpu=cortex-a78ae+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A78AE"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A78AE feat-dotprod
+#as: -mcpu=cortex-a78ae
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A78AE"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A78AE feat-fp16
+#as: -mcpu=cortex-a78ae
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A78AE"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A78C Attributes
+#as: -mcpu=cortex-a78c+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A78C"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A78C feat-dotprod
+#as: -mcpu=cortex-a78c
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A78C"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A78C feat-fp16
+#as: -mcpu=cortex-a78c
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A78C"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-A8 Attributes
+#as: -mcpu=cortex-a8+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A8"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_Virtualization_use: TrustZone
--- /dev/null
+#name: Cortex-A8 feat-simd
+#as: -mcpu=cortex-a8
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A8"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv3
+ Tag_Advanced_SIMD_arch: NEONv1
+ Tag_Virtualization_use: TrustZone
--- /dev/null
+#name: Cortex-A9 Attributes
+#as: -mcpu=cortex-a9+nofp+nosimd
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A9"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone
--- /dev/null
+#name: Cortex-A9 feat-mp
+#as: -mcpu=cortex-a9
+#source: feat-mp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A9"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv4
+ Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone
--- /dev/null
+#name: Cortex-A9 feat-neon-fp16
+#as: -mcpu=cortex-a9
+#source: feat-neon-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A9"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv4
+ Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone
--- /dev/null
+#name: Cortex-A9 feat-sec
+#as: -mcpu=cortex-a9
+#source: feat-sec.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-A9"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv4
+ Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone
--- /dev/null
+#name: Cortex-M33 Attributes
+#as: -mcpu=cortex-m33+nofp+nodsp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M33"
+ Tag_CPU_arch: v8-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
--- /dev/null
+#name: Cortex-M33 feat-dsp
+#as: -mcpu=cortex-m33
+#source: feat-dsp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M33"
+ Tag_CPU_arch: v8-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
+ Tag_FP_arch: VFPv4-D16
+ Tag_DSP_extension: Allowed
--- /dev/null
+#name: Cortex-M33 feat-fp-vfpv5
+#as: -mcpu=cortex-m33
+#source: feat-fp-vfpv5.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M33"
+ Tag_CPU_arch: v8-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
+ Tag_FP_arch: VFPv4-D16
+ Tag_DSP_extension: Allowed
--- /dev/null
+#name: Cortex-M35P Attributes
+#as: -mcpu=cortex-m35p+nofp+nodsp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M35P"
+ Tag_CPU_arch: v8-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
--- /dev/null
+#name: Cortex-M35P feat-dsp
+#as: -mcpu=cortex-m35p
+#source: feat-dsp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M35P"
+ Tag_CPU_arch: v8-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
+ Tag_FP_arch: VFPv4-D16
+ Tag_DSP_extension: Allowed
--- /dev/null
+#name: Cortex-M35P feat-fp-vfpv5
+#as: -mcpu=cortex-m35p
+#source: feat-fp-vfpv5.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M35P"
+ Tag_CPU_arch: v8-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
+ Tag_FP_arch: VFPv4-D16
+ Tag_DSP_extension: Allowed
--- /dev/null
+#name: Cortex-M4 Attributes
+#as: -mcpu=cortex-m4+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M4"
+ Tag_CPU_arch: v7E-M
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Thumb-2
--- /dev/null
+#name: Cortex-M4 feat-fp-vfpv3
+#as: -mcpu=cortex-m4
+#source: feat-fp-vfpv3.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M4"
+ Tag_CPU_arch: v7E-M
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv4-D16
+ Tag_ABI_HardFP_use: SP only
--- /dev/null
+#name: Cortex-M52 Attributes
+#as: -mcpu=cortex-m52+nopacbti+nomve.fp+nomve+nofp+nodsp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M52"
+ Tag_CPU_arch: v8.1-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
+ Tag_DSP_extension: Allowed
--- /dev/null
+#name: Cortex-M52 Attributes 1
+#as: -mcpu=cortex-m52+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M52"
+ Tag_CPU_arch: v8.1-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
+ Tag_FP_arch: FPv5/FP-D16 for ARMv8
+ Tag_DSP_extension: Allowed
+ Tag_MVE_arch: MVE Integer and FP
--- /dev/null
+#name: Cortex-M52 feat-fp.dp
+#as: -mcpu=cortex-m52
+#source: feat-fp.dp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M52"
+ Tag_CPU_arch: v8.1-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
+ Tag_FP_arch: FPv5/FP-D16 for ARMv8
+ Tag_DSP_extension: Allowed
+ Tag_MVE_arch: MVE Integer and FP
--- /dev/null
+#name: Cortex-M52 feat-mve.fp
+#as: -mcpu=cortex-m52
+#source: feat-mve.fp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M52"
+ Tag_CPU_arch: v8.1-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
+ Tag_FP_arch: FPv5/FP-D16 for ARMv8
+ Tag_DSP_extension: Allowed
+ Tag_MVE_arch: MVE Integer and FP
--- /dev/null
+#name: Cortex-M52 feat-pacbti
+#as: -mcpu=cortex-m52
+#source: feat-pacbti.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M52"
+ Tag_CPU_arch: v8.1-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
+ Tag_FP_arch: FPv5/FP-D16 for ARMv8
+ Tag_DSP_extension: Allowed
+ Tag_MVE_arch: MVE Integer and FP
--- /dev/null
+#name: Cortex-M55 Attributes
+#as: -mcpu=cortex-m55+nomve.fp+nomve+nofp+nodsp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M55"
+ Tag_CPU_arch: v8.1-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
+ Tag_DSP_extension: Allowed
--- /dev/null
+#name: Cortex-M55 Attributes 1
+#as: -mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M55"
+ Tag_CPU_arch: v8.1-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
+ Tag_FP_arch: FPv5/FP-D16 for ARMv8
+ Tag_DSP_extension: Allowed
+ Tag_MVE_arch: MVE Integer and FP
--- /dev/null
+#name: Cortex-M55 feat-fp.dp
+#as: -mcpu=cortex-m55
+#source: feat-fp.dp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M55"
+ Tag_CPU_arch: v8.1-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
+ Tag_FP_arch: FPv5/FP-D16 for ARMv8
+ Tag_DSP_extension: Allowed
+ Tag_MVE_arch: MVE Integer and FP
--- /dev/null
+#name: Cortex-M55 feat-mve.fp
+#as: -mcpu=cortex-m55
+#source: feat-mve.fp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M55"
+ Tag_CPU_arch: v8.1-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
+ Tag_FP_arch: FPv5/FP-D16 for ARMv8
+ Tag_DSP_extension: Allowed
+ Tag_MVE_arch: MVE Integer and FP
--- /dev/null
+#name: Cortex-M7 Attributes
+#as: -mcpu=cortex-m7+nofp+nofp.dp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M7"
+ Tag_CPU_arch: v7E-M
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Thumb-2
--- /dev/null
+#name: Cortex-M7 feat-fp.dp
+#as: -mcpu=cortex-m7
+#source: feat-fp.dp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M7"
+ Tag_CPU_arch: v7E-M
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FPv5/FP-D16 for ARMv8
--- /dev/null
+#name: Cortex-M85 Attributes
+#as: -mcpu=cortex-m85+nopacbti+nomve.fp+nomve+nofp+nodsp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M85"
+ Tag_CPU_arch: v8.1-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
+ Tag_DSP_extension: Allowed
--- /dev/null
+#name: Cortex-M85 feat-fp.dp
+#as: -mcpu=cortex-m85
+#source: feat-fp.dp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M85"
+ Tag_CPU_arch: v8.1-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
+ Tag_FP_arch: FPv5/FP-D16 for ARMv8
+ Tag_DSP_extension: Allowed
+ Tag_MVE_arch: MVE Integer and FP
--- /dev/null
+#name: Cortex-M85 feat-mve.fp
+#as: -mcpu=cortex-m85
+#source: feat-mve.fp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M85"
+ Tag_CPU_arch: v8.1-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
+ Tag_FP_arch: FPv5/FP-D16 for ARMv8
+ Tag_DSP_extension: Allowed
+ Tag_MVE_arch: MVE Integer and FP
--- /dev/null
+#name: Cortex-M85 feat-pacbti
+#as: -mcpu=cortex-m85
+#source: feat-pacbti.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-M85"
+ Tag_CPU_arch: v8.1-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
+ Tag_FP_arch: FPv5/FP-D16 for ARMv8
+ Tag_DSP_extension: Allowed
+ Tag_MVE_arch: MVE Integer and FP
--- /dev/null
+#name: Cortex R4F feat-fp-vfpv3
+#as: -mcpu=cortex-r4f
+#source: feat-fp-vfpv3.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-R4F"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv3-D16
--- /dev/null
+#name: Cortex-R5 Attributes
+#as: -mcpu=cortex-r5+nofp+nofp.dp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-R5"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_DIV_use: Allowed in v7-A with integer division extension
--- /dev/null
+#name: Cortex-R5 feat-fp-vfpv3
+#as: -mcpu=cortex-r5
+#source: feat-fp-vfpv3.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-R5"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv3
+ Tag_DIV_use: Allowed in v7-A with integer division extension
--- /dev/null
+#name: Cortex-R5 feat-idiv
+#as: -mcpu=cortex-r5
+#source: feat-idiv.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-R5"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv3
+ Tag_DIV_use: Allowed in v7-A with integer division extension
--- /dev/null
+#name: Cortex-R52 Attributes
+#as: -mcpu=cortex-r52+nofp.dp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-R52"
+ Tag_CPU_arch: v8-R
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FPv5/FP-D16 for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-R52 feat-crc
+#as: -mcpu=cortex-r52
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-R52"
+ Tag_CPU_arch: v8-R
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-R52 feat-simd
+#as: -mcpu=cortex-r52
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-R52"
+ Tag_CPU_arch: v8-R
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-R52plus Attributes
+#as: -mcpu=cortex-r52plus+nofp.dp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-R52\+"
+ Tag_CPU_arch: v8-R
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FPv5/FP-D16 for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-R52plus feat-crc
+#as: -mcpu=cortex-r52plus
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-R52\+"
+ Tag_CPU_arch: v8-R
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-R52plus feat-simd
+#as: -mcpu=cortex-r52plus
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-R52\+"
+ Tag_CPU_arch: v8-R
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-R7 Attributes
+#as: -mcpu=cortex-r7+nofp+nofp.dp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-R7"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_DIV_use: Allowed in v7-A with integer division extension
--- /dev/null
+#name: Cortex-R7 feat-idiv
+#as: -mcpu=cortex-r7
+#source: feat-idiv.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-R7"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv3-D16
+ Tag_FP_HP_extension: Allowed
+ Tag_DIV_use: Allowed in v7-A with integer division extension
--- /dev/null
+#name: Cortex-R7 feat-vfpv3-d16-fp16
+#as: -mcpu=cortex-r7
+#source: feat-vfpv3-d16-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-R7"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv3-D16
+ Tag_FP_HP_extension: Allowed
+ Tag_DIV_use: Allowed in v7-A with integer division extension
--- /dev/null
+#name: Cortex-R8 Attributes
+#as: -mcpu=cortex-r8+nofp+nofp.dp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-R8"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_DIV_use: Allowed in v7-A with integer division extension
--- /dev/null
+#name: Cortex-R8 feat-idiv
+#as: -mcpu=cortex-r8
+#source: feat-idiv.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-R8"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv3-D16
+ Tag_FP_HP_extension: Allowed
+ Tag_DIV_use: Allowed in v7-A with integer division extension
--- /dev/null
+#name: Cortex-R8 feat-vfpv3-d16-fp16
+#as: -mcpu=cortex-r8
+#source: feat-vfpv3-d16-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-R8"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv3-D16
+ Tag_FP_HP_extension: Allowed
+ Tag_DIV_use: Allowed in v7-A with integer division extension
--- /dev/null
+#name: Cortex-X1 Attributes
+#as: -mcpu=cortex-x1+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-X1"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-X1 feat-dotprod
+#as: -mcpu=cortex-x1
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-X1"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-X1 feat-fp16
+#as: -mcpu=cortex-x1
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-X1"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-X1C Attributes
+#as: -mcpu=cortex-x1c+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-X1C"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-X1C feat-dotprod
+#as: -mcpu=cortex-x1c
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-X1C"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Cortex-X1C feat-fp16
+#as: -mcpu=cortex-x1c
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Cortex-X1C"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Exynos-M1 Attributes
+#as: -mcpu=exynos-m1+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Samsung Exynos M1"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Exynos-M1 feat-crc
+#as: -mcpu=exynos-m1
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Samsung Exynos M1"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Exynos-M1 feat-simd
+#as: -mcpu=exynos-m1
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Samsung Exynos M1"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Marvell-PJ4 feat-fp-vfpv3
+#as: -mcpu=marvell-pj4
+#source: feat-fp-vfpv3.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "MARVELL-PJ4"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv3
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone
--- /dev/null
+#name: Marvell-PJ4 feat-mp
+#as: -mcpu=marvell-pj4
+#source: feat-mp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "MARVELL-PJ4"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv3
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone
--- /dev/null
+#name: Marvell-PJ4 feat-sec
+#as: -mcpu=marvell-pj4
+#source: feat-sec.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "MARVELL-PJ4"
+ Tag_CPU_arch: v7
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: VFPv3
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone
--- /dev/null
+#name: Neoverse-N1 Attributes
+#as: -mcpu=neoverse-n1+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Neoverse N1"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Neoverse-N1 feat-dotprod
+#as: -mcpu=neoverse-n1
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Neoverse N1"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Neoverse-N1 feat-fp16
+#as: -mcpu=neoverse-n1
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Neoverse N1"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Neoverse-N2 Attributes
+#as: -mcpu=neoverse-n2+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Neoverse N2"
+ Tag_CPU_arch: v9
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Neoverse-N2 feat-bf16
+#as: -mcpu=neoverse-n2
+#source: feat-bf16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Neoverse N2"
+ Tag_CPU_arch: v9
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Neoverse-N2 feat-fp16
+#as: -mcpu=neoverse-n2
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Neoverse N2"
+ Tag_CPU_arch: v9
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Neoverse-N2 feat-i8mm
+#as: -mcpu=neoverse-n2
+#source: feat-i8mm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Neoverse N2"
+ Tag_CPU_arch: v9
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Neoverse-V1 Attributes
+#as: -mcpu=neoverse-v1+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Neoverse V1"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Neoverse-V1 feat-bf16
+#as: -mcpu=neoverse-v1
+#source: feat-bf16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Neoverse V1"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Neoverse-V1 feat-fp16
+#as: -mcpu=neoverse-v1
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Neoverse V1"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: Neoverse-V1 feat-i8mm
+#as: -mcpu=neoverse-v1
+#source: feat-i8mm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "Neoverse V1"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+#name: XGene1 feat-simd
+#as: -mcpu=xgene1
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "APM X-Gene 1"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
projects / thirdparty / binutils-gdb.git / commitdiff
