net: mediatek: fix sgmii selection for mt7622

Unlike other platforms, mt7622 has only one SGMII and it can be
attached to either gmac1 or gmac2. So the register field of the
sgmii selection differs from other platforms as newer platforms can
control each sgmii individually.

This patch adds a new capability for mt7622 to handle this case.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
index b8cb1f6499517bdeb7737f3ff9fac2c9eb85b53c..592764df3d1e750dae24b493f53a8a0347ef5713 100644 (file)
--- a/drivers/net/mtk_eth.c
+++ b/drivers/net/mtk_eth.c
@@ -1434,7 +1434,7 @@ static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv)
 
 static void mtk_mac_init(struct mtk_eth_priv *priv)
 {
-       int i, ge_mode = 0;
+       int i, sgmii_sel_mask = 0, ge_mode = 0;
        u32 mcr;
 
        switch (priv->phy_interface) {
@@ -1450,8 +1450,13 @@ static void mtk_mac_init(struct mtk_eth_priv *priv)
                }
 
                ge_mode = GE_MODE_RGMII;
-               mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, SYSCFG1_SGMII_SEL_M,
+
+               if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII))
+                       sgmii_sel_mask = SYSCFG1_SGMII_SEL_M;
+
+               mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, sgmii_sel_mask,
                               SYSCFG1_SGMII_SEL(priv->gmac_id));
+
                if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
                        mtk_sgmii_an_init(priv);
                else
@@ -2112,6 +2117,7 @@ static const struct mtk_soc_data mt7623_data = {
 };
 
 static const struct mtk_soc_data mt7622_data = {
+       .caps = MT7622_CAPS,
        .ana_rgc3 = 0x2028,
        .gdma_count = 2,
        .pdma_base = PDMA_V1_BASE,

diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h
index 896dd6636c76cd5efc059364d156ac79f373706f..ad079b5263b20bfa98e063402b6c7c7483436678 100644 (file)
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -23,6 +23,7 @@ enum mkt_eth_capabilities {
        /* PATH BITS */
        MTK_ETH_PATH_GMAC1_TRGMII_BIT,
        MTK_ETH_PATH_GMAC2_SGMII_BIT,
+       MTK_ETH_PATH_MT7622_SGMII_BIT,
 };
 
 #define MTK_TRGMII                     BIT(MTK_TRGMII_BIT)
@@ -36,6 +37,7 @@ enum mkt_eth_capabilities {
 #define MTK_ETH_PATH_GMAC1_TRGMII      BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
 
 #define MTK_ETH_PATH_GMAC2_SGMII       BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
+#define MTK_ETH_PATH_MT7622_SGMII      BIT(MTK_ETH_PATH_MT7622_SGMII_BIT)
 
 #define MTK_GMAC1_TRGMII       (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
 
@@ -45,6 +47,8 @@ enum mkt_eth_capabilities {
 
 #define MT7621_CAPS  (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
 
+#define MT7622_CAPS  (MTK_ETH_PATH_MT7622_SGMII)
+
 #define MT7623_CAPS  (MTK_GMAC1_TRGMII)
 
 #define MT7981_CAPS  (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2)
@@ -68,8 +72,8 @@ enum mkt_eth_capabilities {
 #define ETHSYS_SYSCFG1_REG             0x14
 #define SYSCFG1_GE_MODE_S(n)           (12 + ((n) * 2))
 #define SYSCFG1_GE_MODE_M              0x3
-#define SYSCFG1_SGMII_SEL_M            (0x3 << 8)
-#define SYSCFG1_SGMII_SEL(gmac)                ((!(gmac)) ? BIT(9) : BIT(8))
+#define SYSCFG1_SGMII_SEL_M            GENMASK(9, 8)
+#define SYSCFG1_SGMII_SEL(gmac)                BIT(9 - (gmac))
 
 #define ETHSYS_CLKCFG0_REG             0x2c
 #define ETHSYS_TRGMII_CLK_SEL362_5     BIT(11)