drm/amd/display: Query DC for gfx handling when setting linear tiling

[Why]
Post-driver cases always use linear tiling yet gfx handling for this
case is improper, allowing for incorrect gfx structs to be populated and
used.

[How]
Query DC for the apporpriate linear tiling mode and populate the DCN
specific gfx version structs.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Nicholas Carbones <Nicholas.Carbones@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 31589f22aae0ea9ffdbc120cd23480289c0db472..8b9c686eefd25b38bbb7fa146dab428675e8ec38 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2617,6 +2617,16 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)
        dc->optimized_required = false;
 }
 
+void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info)
+{
+       if (!dc || !tiling_info)
+               return;
+       if (dc->res_pool && dc->res_pool->funcs && dc->res_pool->funcs->get_default_tiling_info) {
+               dc->res_pool->funcs->get_default_tiling_info(tiling_info);
+               return;
+       }
+}
+
 bool dc_set_generic_gpio_for_stereo(bool enable,
                struct gpio_service *gpio_service)
 {

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index c7a09724f5693ed87ffcfa1f1edad90a00714546..1e5c3a2bfaeff47ee7dc3e37bcb2325d366709bd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1970,6 +1970,15 @@ void dc_plane_cm_retain(struct dc_plane_cm *cm);
 void dc_post_update_surfaces_to_stream(
                struct dc *dc);
 
+/*
+ * dc_get_default_tiling_info() - Retrieve an ASIC-appropriate default tiling
+ * description for (typically) linear surfaces.
+ *
+ * This is used by OS/DM paths that need a valid, fully-initialized tiling
+ * description without hardcoding gfx-version specifics in the caller.
+ */
+void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info);
+
 /**
  * struct dc_validation_set - Struct to store surface/stream associations for validation
  */

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 43579b0e1482526c4a898e95a176a9cda5341272..e960ca9062adcc587439c613c0c9274c8899a7b9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -214,6 +214,7 @@ struct resource_funcs {
             unsigned int index);
 
        void (*get_panel_config_defaults)(struct dc_panel_config *panel_config);
+       void (*get_default_tiling_info)(struct dc_tiling_info *tiling_info);
        void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx);
        /*
         * Get indicator of power from a context that went through full validation

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
index bbe185e15eb679d017f8601a43d51309d199d2cb..44178e915bdcb8d0d6c645f2879ce6f1b7bcac55 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
@@ -1273,6 +1273,12 @@ static const struct dc_cap_funcs cap_funcs = {
        .get_dcc_compression_cap = dcn10_get_dcc_compression_cap
 };
 
+void dcn10_get_default_tiling_info(struct dc_tiling_info *tiling_info)
+{
+       tiling_info->gfxversion = DcGfxVersion9;
+       tiling_info->gfx9.swizzle = DC_SW_LINEAR;
+}
+
 static const struct resource_funcs dcn10_res_pool_funcs = {
        .destroy = dcn10_destroy_resource_pool,
        .link_enc_create = dcn10_link_encoder_create,
@@ -1284,7 +1290,8 @@ static const struct resource_funcs dcn10_res_pool_funcs = {
        .add_stream_to_ctx = dcn10_add_stream_to_ctx,
        .patch_unknown_plane_state = dcn10_patch_unknown_plane_state,
        .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
-       .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
+       .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
+       .get_default_tiling_info = dcn10_get_default_tiling_info
 };
 
 static uint32_t read_pipe_fuses(struct dc_context *ctx)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h
index 7bc1be53e8009664f9d924492ff41ec7e18707c4..c7409298caa9a9784a2f5303d6acea10debe8719 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h
@@ -53,5 +53,7 @@ struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
 
 unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx);
 
+void dcn10_get_default_tiling_info(struct dc_tiling_info *tiling_info);
+
 #endif /* __DC_RESOURCE_DCN10_H__ */
 

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
index 366576b1c617c3aad8fae5af029746f367108944..8426d5f9f3771e887cd0e5d25ac502d4279c255b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
@@ -2232,7 +2232,8 @@ static const struct resource_funcs dcn20_res_pool_funcs = {
        .set_mcif_arb_params = dcn20_set_mcif_arb_params,
        .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
        .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
-       .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
+       .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
+       .get_default_tiling_info = dcn10_get_default_tiling_info
 };
 
 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
index 4ea76e46ab15de2036f22ff58465547ea111522c..491d8d3b1b68b50460b6c60bda569c509dbda46d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c
@@ -1081,7 +1081,8 @@ static struct resource_funcs dcn201_res_pool_funcs = {
        .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
        .set_mcif_arb_params = dcn20_set_mcif_arb_params,
        .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
-       .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
+       .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
+       .get_default_tiling_info = dcn10_get_default_tiling_info
 };
 
 static bool dcn201_resource_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
index 0f4307f8f3dd595d95cdb45dfeaecc3a87bc67bf..a1a529cabb93041a2c2b6aa12da012133cb4846d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
@@ -1378,7 +1378,8 @@ static const struct resource_funcs dcn21_res_pool_funcs = {
        .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
        .update_bw_bounding_box = dcn21_update_bw_bounding_box,
        .get_panel_config_defaults = dcn21_get_panel_config_defaults,
-       .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
+       .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
+       .get_default_tiling_info = dcn10_get_default_tiling_info
 };
 
 static bool dcn21_resource_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
index 2fa86b9587ed00638cb96dd66b026e5b5eeaf08f..566517b99a097462f7907e698ee311a8c6940431 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
@@ -2248,7 +2248,8 @@ static const struct resource_funcs dcn30_res_pool_funcs = {
        .update_bw_bounding_box = dcn30_update_bw_bounding_box,
        .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
        .get_panel_config_defaults = dcn30_get_panel_config_defaults,
-       .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
+       .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
+       .get_default_tiling_info = dcn10_get_default_tiling_info
 };
 
 #define CTX ctx

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
index 7842bee57e636cd4cd34a0bb23cd5b96a6b863cb..d21b928055e5cb7ac4fd8c787bcb269a0eab717d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
@@ -1400,7 +1400,8 @@ static struct resource_funcs dcn301_res_pool_funcs = {
        .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
        .update_bw_bounding_box = dcn301_update_bw_bounding_box,
        .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
-       .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
+       .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
+       .get_default_tiling_info = dcn10_get_default_tiling_info,
 };
 
 static bool dcn301_resource_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
index 1874d5d6b782002557f8ac752c4dcf9b5e112be3..d24b9b81df77e0f402f8235d0dcf24505332ea28 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
@@ -1155,7 +1155,8 @@ static struct resource_funcs dcn302_res_pool_funcs = {
                .update_bw_bounding_box = dcn302_update_bw_bounding_box,
                .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
                .get_panel_config_defaults = dcn302_get_panel_config_defaults,
-               .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
+               .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
+               .get_default_tiling_info = dcn10_get_default_tiling_info
 };
 
 static struct dc_cap_funcs cap_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
index d52201cb359fd5ab74881eb23842b32cb4884c50..0b44a33a0d326fcb1453359e5b5222969f7dabdd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
@@ -1099,7 +1099,8 @@ static struct resource_funcs dcn303_res_pool_funcs = {
                .update_bw_bounding_box = dcn303_update_bw_bounding_box,
                .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
                .get_panel_config_defaults = dcn303_get_panel_config_defaults,
-               .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
+               .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
+               .get_default_tiling_info = dcn10_get_default_tiling_info
 };
 
 static struct dc_cap_funcs cap_funcs = {

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
index 2055f1f8af6521fa47ad9968a1bce9464182f474..046724c86c7ae794bca47032ee6ac0e30e91c1c6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
@@ -1851,6 +1851,7 @@ static struct resource_funcs dcn31_res_pool_funcs = {
        .get_det_buffer_size = dcn31_get_det_buffer_size,
        .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
        .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
+       .get_default_tiling_info = dcn10_get_default_tiling_info,
        .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
index 1939f720ba29573fa2cdd1a82c1abcca4520f20a..66bf7725aeaf093bb08c770f8f6f50cb9bfb795e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
@@ -1782,7 +1782,8 @@ static struct resource_funcs dcn314_res_pool_funcs = {
        .get_det_buffer_size = dcn31_get_det_buffer_size,
        .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
        .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
-       .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params
+       .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
+       .get_default_tiling_info = dcn10_get_default_tiling_info
 };
 
 static struct clock_source *dcn30_clock_source_create(

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
index e8377c190f635e30518ac9c1f644e8d54a19a2ba..4d5fcd7a0b00678468825352705be3f57070ccd3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
@@ -1846,7 +1846,8 @@ static struct resource_funcs dcn315_res_pool_funcs = {
        .get_det_buffer_size = dcn31_get_det_buffer_size,
        .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
        .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
-       .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params
+       .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
+       .get_default_tiling_info = dcn10_get_default_tiling_info
 };
 
 static bool dcn315_resource_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
index 045ce01bd74eb1ebcce9a174544b64c99d11ddb2..63675b53674af505fe5ebe4985322b6e817bb1d8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
@@ -1721,7 +1721,8 @@ static struct resource_funcs dcn316_res_pool_funcs = {
        .get_det_buffer_size = dcn31_get_det_buffer_size,
        .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
        .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
-       .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params
+       .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
+       .get_default_tiling_info = dcn10_get_default_tiling_info
 };
 
 static bool dcn316_resource_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
index c7fd604024d6452d2b6daef5dc86d7427c923de7..2b9d8d2245723145b05efd1d3a741402012b05a0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
@@ -2112,6 +2112,7 @@ static struct resource_funcs dcn32_res_pool_funcs = {
        .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
        .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
        .add_phantom_pipes = dcn32_add_phantom_pipes,
+       .get_default_tiling_info = dcn10_get_default_tiling_info,
        .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
        .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
        .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
index c1582c27ac872b4a5a2fb5cf1833de366cc6903b..e3dc4b1aacda88d9934ec0a09669cac29444b0c3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
@@ -1619,6 +1619,7 @@ static struct resource_funcs dcn321_res_pool_funcs = {
        .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
        .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
        .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size,
+       .get_default_tiling_info = dcn10_get_default_tiling_info,
 };
 
 static uint32_t read_pipe_fuses(struct dc_context *ctx)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 3494a40cea99f7047ecbd995ea3dfd1805f1d7ae..ff557c4d594e4929c378ca9cda9dcd310782b168 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -1802,7 +1802,8 @@ static struct resource_funcs dcn35_res_pool_funcs = {
        .get_det_buffer_size = dcn31_get_det_buffer_size,
        .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
        .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
-       .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params
+       .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
+       .get_default_tiling_info = dcn10_get_default_tiling_info
 };
 
 static bool dcn35_resource_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index 080bc7f24ffaacd1a5af2d9ced1eb8d682fd316b..0c39d0b17947011a80ccacbe0b6e934d2bf04dbe 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -1775,7 +1775,8 @@ static struct resource_funcs dcn351_res_pool_funcs = {
        .get_det_buffer_size = dcn31_get_det_buffer_size,
        .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
        .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
-       .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params
+       .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
+       .get_default_tiling_info = dcn10_get_default_tiling_info
 };
 
 static bool dcn351_resource_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
index af51ac4ea59e20e4b1c6c809ae9223653ecb49a0..1ad44fb64213019d450df23474d0e65a7cea3a67 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
@@ -1781,7 +1781,8 @@ static struct resource_funcs dcn36_res_pool_funcs = {
        .get_preferred_eng_id_dpia = dcn36_get_preferred_eng_id_dpia,
        .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
        .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
-       .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params
+       .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
+       .get_default_tiling_info = dcn10_get_default_tiling_info,
 };
 
 static bool dcn36_resource_construct(

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index e37aab939a41bc215205d895ad6f34a1985431fc..60a0e7c95c735c2df5f83f257d92163c25b26f76 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -1839,9 +1839,16 @@ static struct resource_funcs dcn401_res_pool_funcs = {
        .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
        .get_power_profile = dcn401_get_power_profile,
        .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe,
-       .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size
+       .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size,
+       .get_default_tiling_info = dcn401_get_default_tiling_info
 };
 
+void dcn401_get_default_tiling_info(struct dc_tiling_info *tiling_info)
+{
+       tiling_info->gfxversion = DcGfxAddr3;
+       tiling_info->gfx_addr3.swizzle = DC_ADDR3_SW_LINEAR;
+}
+
 static uint32_t read_pipe_fuses(struct dc_context *ctx)
 {
        uint32_t value = REG_READ(CC_DC_PIPE_DIS);

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
index 08bec1755617447e6402c71502662e543fde9fed..5f3b0319cb5bb3d89840fbbaed67a06a2f8c2424 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
@@ -28,6 +28,8 @@ enum dc_status dcn401_validate_bandwidth(struct dc *dc,
 
 void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context);
 
+void dcn401_get_default_tiling_info(struct dc_tiling_info *tiling_info);
+
 unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx);
 
 /* Following are definitions for run time init of reg offsets */