backport: pa.md (memory_barrier): Revise to use ldcw barriers.

	Backport from mainline
	2019-11-07  John David Anglin  <danglin@gcc.gnu.org>

	* config/pa/pa.md (memory_barrier): Revise to use ldcw barriers.
	Enhance comment.
	(memory_barrier_coherent, memory_barrier_64, memory_barrier_32): New
	insn patterns using ldcw instruction.
	(memory_barrier): Remove insn pattern using sync instruction.
	* config/pa/pa.opt (coherent-ldcw): New option.
	(ordered): New option.

From-SVN: r278001

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 64849fa22bbc65cf3d3ac5fe22ed0c5ede6e7ffd..433b7d91d0a2c4a0076e6d5a141cb20a03fbcfaf 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2019-11-09  John David Anglin  <danglin@gcc.gnu.org>
+
+       Backport from mainline
+       2019-11-07  John David Anglin  <danglin@gcc.gnu.org>
+
+       * config/pa/pa.md (memory_barrier): Revise to use ldcw barriers.
+       Enhance comment.
+       (memory_barrier_coherent, memory_barrier_64, memory_barrier_32): New
+       insn patterns using ldcw instruction.
+       (memory_barrier): Remove insn pattern using sync instruction.
+       * config/pa/pa.opt (coherent-ldcw): New option.
+       (ordered): New option.
+
 2019-11-08  Jakub Jelinek  <jakub@redhat.com>
 
        PR c++/92384

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 84630ad536d54fc926bb514aaf64b5178a0e8247..e273cddc01dbd4a48bc576f07fc75ad1416927a6 100644 (file)
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -10091,23 +10091,55 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
    (set_attr "length" "4,16")])
 
 ;; PA 2.0 hardware supports out-of-order execution of loads and stores, so
-;; we need a memory barrier to enforce program order for memory references.
-;; Since we want PA 1.x code to be PA 2.0 compatible, we also need the
-;; barrier when generating PA 1.x code.
+;; we need memory barriers to enforce program order for memory references
+;; when the TLB and PSW O bits are not set.  We assume all PA 2.0 systems
+;; are weakly ordered since neither HP-UX or Linux set the PSW O bit.  Since
+;; we want PA 1.x code to be PA 2.0 compatible, we also need barriers when
+;; generating PA 1.x code even though all PA 1.x systems are strongly ordered.
+
+;; When barriers are needed, we use a strongly ordered ldcw instruction as
+;; the barrier.  Most PA 2.0 targets are cache coherent.  In that case, we
+;; can use the coherent cache control hint and avoid aligning the ldcw
+;; address.  In spite of its description, it is not clear that the sync
+;; instruction works as a barrier.
 
 (define_expand "memory_barrier"
-  [(set (match_dup 0)
-        (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))]
+  [(parallel
+     [(set (match_dup 0) (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))
+      (clobber (match_dup 1))])]
   ""
 {
-  operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+  /* We don't need a barrier if the target uses ordered memory references.  */
+  if (TARGET_ORDERED)
+    FAIL;
+  operands[1] = gen_reg_rtx (Pmode);
+  operands[0] = gen_rtx_MEM (BLKmode, operands[1]);
   MEM_VOLATILE_P (operands[0]) = 1;
 })
 
-(define_insn "*memory_barrier"
+(define_insn "*memory_barrier_coherent"
   [(set (match_operand:BLK 0 "" "")
-        (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))]
-  ""
-  "sync"
+        (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))
+   (clobber (match_operand 1 "pmode_register_operand" "=r"))]
+  "TARGET_PA_20 && TARGET_COHERENT_LDCW"
+  "ldcw,co 0(%%sp),%1"
   [(set_attr "type" "binary")
    (set_attr "length" "4")])
+
+(define_insn "*memory_barrier_64"
+  [(set (match_operand:BLK 0 "" "")
+        (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))
+    (clobber (match_operand 1 "pmode_register_operand" "=&r"))]
+  "TARGET_64BIT"
+  "ldo 15(%%sp),%1\n\tdepd %%r0,63,3,%1\n\tldcw 0(%1),%1"
+  [(set_attr "type" "binary")
+   (set_attr "length" "12")])
+
+(define_insn "*memory_barrier_32"
+  [(set (match_operand:BLK 0 "" "")
+        (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))
+    (clobber (match_operand 1 "pmode_register_operand" "=&r"))]
+  ""
+  "ldo 15(%%sp),%1\n\t{dep|depw} %%r0,31,3,%1\n\tldcw 0(%1),%1"
+  [(set_attr "type" "binary")
+   (set_attr "length" "12")])

diff --git a/gcc/config/pa/pa.opt b/gcc/config/pa/pa.opt
index b32b3d8abc062511b82becb3dcbf19424e13aeaf..4cb811099332b733dc735e1cec379b92c09e8c58 100644 (file)
--- a/gcc/config/pa/pa.opt
+++ b/gcc/config/pa/pa.opt
@@ -45,6 +45,10 @@ mcaller-copies
 Target Report Mask(CALLER_COPIES)
 Caller copies function arguments passed by hidden reference.
 
+mcoherent-ldcw
+Target Report Var(TARGET_COHERENT_LDCW) Init(1)
+Use ldcw/ldcd coherent cache-control hint.
+
 mdisable-fpregs
 Target Report Mask(DISABLE_FPREGS)
 Disable FP regs.
@@ -90,6 +94,10 @@ mno-space-regs
 Target RejectNegative Report Mask(NO_SPACE_REGS)
 Disable space regs.
 
+mordered
+Target Report Var(TARGET_ORDERED) Init(0)
+Assume memory references are ordered and barriers are not needed.
+
 mpa-risc-1-0
 Target RejectNegative
 Generate PA1.0 code.