amd-drm-next-6.20-2026-01-09:
amdgpu:
- GPUVM updates
- Initial support for larger GPU address spaces
- Initial SMUIO 15.x support
- Documentation updates
- Initial PSP 15.x support
- Initial IH 7.1 support
- Initial IH 6.1.1 support
- SMU 13.0.12 updates
- RAS updates
- Initial MMHUB 3.4 support
- Initial MMHUB 4.2 support
- Initial GC 12.1 support
- Initial GC 11.5.4 support
- HDMI fixes
- Panel replay improvements
- DML updates
- DC FP fixes
- Initial SDMA 6.1.4 support
- Initial SDMA 7.1 support
- Userq updates
- DC HPD refactor
- SwSMU cleanups and refactoring
- TTM memory ops parallelization
- DCN 3.5 fixes
- DP audio fixes
- Clang fixes
- Misc spelling fixes and cleanups
- Initial SDMA 7.11.4 support
- Convert legacy DRM logging helpers to new drm logging helpers
- Initial JPEG 5.3 support
- Add support for changing UMA size via the driver
- DC analog fixes
- GC 9 gfx queue reset support
- Initial SMU 15.x support
amdkfd:
- Reserved SDMA rework
- Refactor SPM
- Initial GC 12.1 support
- Initial GC 11.5.4 support
- Initial SDMA 7.1 support
- Initial SDMA 6.1.4 support
- Increase the kfd process hash table
- Per context support
- Topology fixes
radeon:
- Convert legacy DRM logging helpers to new drm logging helpers
- Use devm for i2c adapters
- Variable sized array fix
- Misc cleanups
UAPI:
- KFD context support. Proposed userspace:
https://github.com/ROCm/rocm-systems/pull/1705
https://github.com/ROCm/rocm-systems/pull/1701
- Add userq metadata queries for more queue types. Proposed userspace:
https://gitlab.freedesktop.org/yogeshmohan/mesa/-/commits/userq_query
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patch.msgid.link/20260109154713.3242957-1-alexander.deucher@amd.com
Signed-off-by: Dave Airlie <airlied@redhat.com>
var SQ_WAVE_SCHED_MODE_DEP_MODE_SIZE = 2
var BARRIER_STATE_SIGNAL_OFFSET = 16
+ var BARRIER_STATE_MEMBER_OFFSET = 4
+ var BARRIER_STATE_MEMBER_SIZE = 7
var BARRIER_STATE_VALID_OFFSET = 0
-var TTMP11_SCHED_MODE_SHIFT = 26
-var TTMP11_SCHED_MODE_SIZE = 2
-var TTMP11_SCHED_MODE_MASK = 0xC000000
-
+ var NAMED_BARRIERS_SR_OFFSET_FROM_HWREG = 0x80
+ var S_BARRIER_INIT_MEMBERCNT_MASK = 0x7F0000
+ var S_BARRIER_INIT_MEMBERCNT_SHIFT = 0x10
+
+ var SQ_WAVE_XNACK_STATE_PRIV_FIRST_REPLAY_SHIFT = 18
+ var SQ_WAVE_XNACK_STATE_PRIV_FIRST_REPLAY_SIZE = 1
+ var SQ_WAVE_XNACK_STATE_PRIV_REPLAY_W64H_SHIFT = 16
+ var SQ_WAVE_XNACK_STATE_PRIV_REPLAY_W64H_SIZE = 1
+ var SQ_WAVE_XNACK_STATE_PRIV_FXPTR_SHIFT = 0
+ var SQ_WAVE_XNACK_STATE_PRIV_FXPTR_SIZE = 7
+
+ #if HAVE_BANKED_VGPRS
+ var SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SHIFT = 12
+ var SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SIZE = 6
+ #endif
+
+var TTMP11_SCHED_MODE_SHIFT = 26
+var TTMP11_SCHED_MODE_SIZE = 2
+var TTMP11_SCHED_MODE_MASK = 0xC000000
var TTMP11_DEBUG_TRAP_ENABLED_SHIFT = 23
var TTMP11_DEBUG_TRAP_ENABLED_MASK = 0x800000
+ var TTMP11_FIRST_REPLAY_SHIFT = 22
+ var TTMP11_FIRST_REPLAY_MASK = 0x400000
+ var TTMP11_REPLAY_W64H_SHIFT = 21
+ var TTMP11_REPLAY_W64H_MASK = 0x200000
+ var TTMP11_FXPTR_SHIFT = 14
+ var TTMP11_FXPTR_MASK = 0x1FC000
// SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14]
// when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE
ef = dma_fence_get_rcu_safe(&p->ef);
rcu_read_unlock();
if (!ef)
- return -EINVAL;
+ return true;
- ret = dma_fence_signal(ef);
+ ret = dma_fence_check_and_signal(ef);
dma_fence_put(ef);
return ret;