sse.md (sse3_mwait): Swap the operand constriants.

2015-06-05  Venkataramanan Kumar  <venkataramanan.kumar@amd.com>

        * config/i386/sse.md (sse3_mwait): Swap the operand constriants.

From-SVN: r224147

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 10676df506ce659ddaa150a7cfcb5671b7001a19..97d90074cf779bbef2d9b84ca5b2fb50f427092c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2015-06-05  Venkataramanan Kumar  <venkataramanan.kumar@amd.com>
+
+       * config/i386/sse.md (sse3_mwait): Swap the operand constriants.
+
 2015-06-03  Jakub Jelinek  <jakub@redhat.com>
 
        Backported from mainline

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 89ead074781c835494dab19f60bd315989ceb44e..4877b73d0ca1417bdc14a7a4c29a18b2aed4b3d4 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -7823,10 +7823,12 @@
    (set_attr "atom_sse_attr" "fence")
    (set_attr "memory" "unknown")])
 
-
+;; As per AMD and Intel ISA manuals, the first operand is extensions
+;; and it goes to %ecx. The second operand received is hints and it goes
+;; to %eax.
 (define_insn "sse3_mwait"
-  [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
-                    (match_operand:SI 1 "register_operand" "c")]
+  [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")
+                    (match_operand:SI 1 "register_operand" "a")]
                    UNSPECV_MWAIT)]
   "TARGET_SSE3"
 ;; 64bit version is "mwait %rax,%rcx". But only lower 32bits are used.