#include "dat.h"
#include "dct.h"
-
/*
* Address Assignment Command
*/
#define CMD_M0_VENDOR_INFO_PRESENT W0_BIT_( 7)
#define CMD_M0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
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/* Data Transfer Speed and Mode */
enum hci_cmd_mode {
MODE_I3C_SDR0 = 0x0,
#include "cmd.h"
#include "xfer_mode_rate.h"
-
/*
* Unified Data Transfer Command
*/
#define CMD_A0_ASSIGN_ADDRESS(v) FIELD_PREP(W0_MASK( 14, 8), v)
#define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
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static unsigned int get_i3c_rate_idx(struct i3c_hci *hci)
{
struct i3c_bus *bus = i3c_master_get_bus(&hci->master);
#include "cmd.h"
#include "dat.h"
-
/*
* Host Controller Capabilities and Operation Registers
*/
#define DEV_CTX_BASE_LO 0x60
#define DEV_CTX_BASE_HI 0x64
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static inline struct i3c_hci *to_i3c_hci(struct i3c_master_controller *m)
{
return container_of(m, struct i3c_hci, master);
#include "hci.h"
#include "dat.h"
-
/*
* Device Address Table Structure
*/
#include "cmd.h"
#include "ibi.h"
-
/*
* Software Parameter Values (somewhat arb itrary for now).
* Some of them could be determined at run time eventually.
#define DATA_BUF_IOC BIT(30) /* Interrupt on Completion */
#define DATA_BUF_BLOCK_SIZE GENMASK(15, 0)
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struct hci_rh_data {
void __iomem *regs;
void *xfer, *resp, *ibi_status, *ibi_data;
#include "ext_caps.h"
#include "xfer_mode_rate.h"
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/* Extended Capability Header */
#define CAP_HEADER_LENGTH GENMASK(23, 8)
#define CAP_HEADER_ID GENMASK(7, 0)
/* MIPI vendor IDs */
#define MIPI_VENDOR_NXP 0x11b
-
int i3c_hci_parse_ext_caps(struct i3c_hci *hci);
#endif
void *vendor_data;
};
-
/*
* Structure to represent a master initiated transfer.
* The rnw, data and data_len fields must be initialized before calling any
kfree(xfer);
}
-
/* This abstracts PIO vs DMA operations */
struct hci_io_ops {
bool (*irq_handler)(struct i3c_hci *hci);
extern const struct hci_io_ops mipi_i3c_hci_pio;
extern const struct hci_io_ops mipi_i3c_hci_dma;
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/* Our per device master private data */
struct i3c_hci_dev_data {
int dat_idx;
void *ibi_data;
};
-
/* list of quirks */
#define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */
#define HCI_QUIRK_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */
#define HCI_QUIRK_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD platforms */
#define HCI_QUIRK_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD platforms */
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/* global functions */
void mipi_i3c_hci_resume(struct i3c_hci *hci);
void mipi_i3c_hci_pio_reset(struct i3c_hci *hci);
#include "cmd.h"
#include "ibi.h"
-
/*
* PIO Access Area
*/