]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
Daily bump.
authorGCC Administrator <gccadmin@gcc.gnu.org>
Fri, 2 Jun 2023 00:17:38 +0000 (00:17 +0000)
committerGCC Administrator <gccadmin@gcc.gnu.org>
Fri, 2 Jun 2023 00:17:38 +0000 (00:17 +0000)
gcc/ChangeLog
gcc/DATESTAMP
gcc/cp/ChangeLog
gcc/fortran/ChangeLog
gcc/testsuite/ChangeLog
libgomp/ChangeLog
libstdc++-v3/ChangeLog

index 734bb4eee9c95e2633d4e2d2dafae5b23f6a0eed..30cf1aa929db529898a04d5ab8b231baf20c59be 100644 (file)
@@ -1,3 +1,89 @@
+2023-06-01  Jason Merrill  <jason@redhat.com>
+
+       * doc/invoke.texi (-Wpedantic): Improve clarity.
+
+2023-06-01  Uros Bizjak  <ubizjak@gmail.com>
+
+       * rtl.h (exp_equiv_p): Change return type from int to bool.
+       * cse.cc (mention_regs): Change return type from int to bool
+       and adjust function body accordingly.
+       (exp_equiv_p): Ditto.
+       (insert_regs): Ditto. Change "modified" function argument to bool
+       and update usage accordingly.
+       (record_jump_cond): Remove always zero "reversed_nonequality"
+       function argument and update usage accordingly.
+       (fold_rtx): Change "changed" variable to bool.
+       (record_jump_equiv): Remove unneeded "reversed_nonequality" variable.
+       (is_dead_reg): Change return type from int to bool.
+
+2023-06-01  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
+
+       * config/xtensa/xtensa.md (adddi3, subdi3):
+       New RTL generation patterns implemented according to the instruc-
+       tion idioms described in the Xtensa ISA reference manual (p. 600).
+
+2023-06-01  Roger Sayle  <roger@nextmovesoftware.com>
+           Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/109973
+       * config/i386/i386-builtin.def (__builtin_ia32_ptestz128): Use new
+       CODE_for_sse4_1_ptestzv2di.
+       (__builtin_ia32_ptestc128): Use new CODE_for_sse4_1_ptestcv2di.
+       (__builtin_ia32_ptestz256): Use new CODE_for_avx_ptestzv4di.
+       (__builtin_ia32_ptestc256): Use new CODE_for_avx_ptestcv4di.
+       * config/i386/i386-expand.cc (ix86_expand_branch): Use CCZmode
+       when expanding UNSPEC_PTEST to compare against zero.
+       * config/i386/i386-features.cc (scalar_chain::convert_compare):
+       Likewise generate CCZmode UNSPEC_PTESTs when converting comparisons.
+       (general_scalar_chain::convert_insn): Use CCZmode for COMPARE result.
+       (timode_scalar_chain::convert_insn): Use CCZmode for COMPARE result.
+       * config/i386/i386-protos.h (ix86_match_ptest_ccmode): Prototype.
+       * config/i386/i386.cc (ix86_match_ptest_ccmode): New predicate to
+       check for suitable matching modes for the UNSPEC_PTEST pattern.
+       * config/i386/sse.md (define_split): When splitting UNSPEC_MOVMSK
+       to UNSPEC_PTEST, preserve the FLAG_REG mode as CCZ.
+       (*<sse4_1>_ptest<mode>): Add asterisk to hide define_insn.  Remove
+       ":CC" mode of FLAGS_REG, instead use ix86_match_ptest_ccmode.
+       (<sse4_1>_ptestz<mode>): New define_expand to specify CCZ.
+       (<sse4_1>_ptestc<mode>): New define_expand to specify CCC.
+       (<sse4_1>_ptest<mode>): A define_expand using CC to preserve the
+       current behavior.
+       (*ptest<mode>_and): Specify CCZ to only perform this optimization
+       when only the Z flag is required.
+
+2023-06-01  Jonathan Wakely  <jwakely@redhat.com>
+
+       PR target/109954
+       * doc/invoke.texi (x86 Options): Fix description of -m32 option.
+
+2023-06-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VDMOV:mode>):
+       Add =r,m and =r,m alternatives.
+       (load_pair<DREG:mode><DREG2:mode>): Likewise.
+       (vec_store_pair<DREG:mode><DREG2:mode>): Likewise.
+
+2023-06-01  Pan Li  <pan2.li@intel.com>
+
+       * common/config/riscv/riscv-common.cc: Add FP_16 mask to zvfhmin
+       and zvfh.
+       * config/riscv/genrvv-type-indexer.cc (valid_type): Allow FP16.
+       (main): Disable FP16 tuple.
+       * config/riscv/riscv-opts.h (MASK_VECTOR_ELEN_FP_16): New macro.
+       (TARGET_VECTOR_ELEN_FP_16): Ditto.
+       * config/riscv/riscv-vector-builtins.cc (check_required_extensions):
+       Add FP16.
+       * config/riscv/riscv-vector-builtins.def (vfloat16mf4_t): New type.
+       (vfloat16mf2_t): Ditto.
+       (vfloat16m1_t): Ditto.
+       (vfloat16m2_t): Ditto.
+       (vfloat16m4_t): Ditto.
+       (vfloat16m8_t): Ditto.
+       * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ELEN_FP_16):
+       New macro.
+       * config/riscv/riscv-vector-switch.def (ENTRY): Allow FP16
+       machine mode based on TARGET_VECTOR_ELEN_FP_16.
+
 2023-06-01  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 
        * config/riscv/riscv-vector-builtins.cc (register_frm): New function.
index e171f9ed053dda5d5afb7b5d7a1d762490bde67c..d0de28459d0b621bccc025e2b26cf56566023a46 100644 (file)
@@ -1 +1 @@
-20230601
+20230602
index 916171bb2144f45db66b0b1a76c81ce910cd0d86..2a132ae3e48fe49b175d5d363041df207d69e0ae 100644 (file)
@@ -1,3 +1,7 @@
+2023-06-01  Jason Merrill  <jason@redhat.com>
+
+       * typeck2.cc (check_narrowing): Check flag_permissive.
+
 2023-05-30  Tobias Burnus  <tobias@codesourcery.com>
 
        PR c/109999
index 72b17c6784cee4aca57e674bcd6ab1c8f970e757..d4e36a3132745fdd7358c97b5db433a7a7fab913 100644 (file)
@@ -1,3 +1,16 @@
+2023-06-01  Harald Anlauf  <anlauf@gmx.de>
+
+       PR fortran/88552
+       * decl.cc (gfc_match_kind_spec): Use error path on missing right
+       parenthesis.
+       (gfc_match_decl_type_spec): Use error return when an error occurred
+       during matching a KIND specifier.
+
+2023-06-01  Tobias Burnus  <tobias@codesourcery.com>
+
+       * parse.cc (decode_omp_directive): Accept all pure directives
+       inside a PURE procedures; handle 'error at(execution).
+
 2023-05-26  Tobias Burnus  <tobias@codesourcery.com>
 
        * dump-parse-tree.cc (show_omp_namelist): Update allocator, fix
index 43e2270b316382a0def51946c8bffa098245f4f8..5ed797a7cfcd8d9d9daa89ab78d5ec65fff99afe 100644 (file)
@@ -1,3 +1,44 @@
+2023-06-01  Harald Anlauf  <anlauf@gmx.de>
+
+       PR fortran/88552
+       * gfortran.dg/pr88552.f90: New test.
+
+2023-06-01  Vineet Gupta  <vineetg@rivosinc.com>
+
+       * lib/torture-options.exp: print the value of non-empty options:
+       torture_without_loops, torture_with_loops, LTO_TORTURE_OPTIONS.
+
+2023-06-01  Vineet Gupta  <vineetg@rivosinc.com>
+
+       * gcc.misc-tests/i386-prefetch.exp: Move early return outside
+       the torture-{init,finish}
+
+2023-06-01  David Edelsohn  <dje.gcc@gmail.com>
+
+       * gcc.target/powerpc/pr100106-sa.c: Skip on AIX.
+       * gcc.target/powerpc/pr109566.c: Skip on AIX.
+
+2023-06-01  Roger Sayle  <roger@nextmovesoftware.com>
+           Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/109973
+       * gcc.target/i386/pr109973-1.c: New test case.
+       * gcc.target/i386/pr109973-2.c: Likewise.
+
+2023-06-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * gcc.target/aarch64/xreg-vec-modes_1.c: New test.
+
+2023-06-01  Tobias Burnus  <tobias@codesourcery.com>
+
+       * gfortran.dg/gomp/nothing-2.f90: Remove one dg-error.
+       * gfortran.dg/gomp/pr79154-2.f90: Update expected dg-error wording.
+       * gfortran.dg/gomp/pr79154-simd.f90: Likewise.
+       * gfortran.dg/gomp/pure-1.f90: New test.
+       * gfortran.dg/gomp/pure-2.f90: New test.
+       * gfortran.dg/gomp/pure-3.f90: New test.
+       * gfortran.dg/gomp/pure-4.f90: New test.
+
 2023-06-01  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 
        * gcc.target/riscv/rvv/base/frm-1.c: New test.
index c320f0455e3cb1c86e0f209233cb0fb3466959d1..51a41906d5c1e87d33cd5e5fb374f956ff8fcdea 100644 (file)
@@ -1,3 +1,7 @@
+2023-06-01  Tobias Burnus  <tobias@codesourcery.com>
+
+       * libgomp.texi (OpenMP 5.2): Mark pure-directive handling as 'Y'.
+
 2023-05-26  Tobias Burnus  <tobias@codesourcery.com>
 
        * testsuite/libgomp.fortran/allocate-4.f90: Update dg-error.
index c684e3430d02217c8f73c1a05992d8ade17aafb7..346eac4708483cf7d96d69df61a811651ef1412a 100644 (file)
@@ -1,3 +1,70 @@
+2023-06-01  Jonathan Wakely  <jwakely@redhat.com>
+
+       * testsuite/26_numerics/pstl/numeric_ops/transform_reduce.cc:
+       Add const to equality operator.
+
+2023-06-01  Jonathan Wakely  <jwakely@redhat.com>
+
+       * include/std/expected (expected::and_then, expected::or_else)
+       (expected::transform_error): Use _M_val and _M_unex instead of
+       calling value() and error(), as per LWG 3938.
+       (expected::transform): Likewise. Remove incorrect std::move
+       calls from lvalue overloads.
+       (expected<void, E>::and_then, expected<void, E>::or_else)
+       (expected<void, E>::transform): Use _M_unex instead of calling
+       error().
+       * testsuite/20_util/expected/lwg3877.cc: Add checks for and_then
+       and transform, and for std::expected<void, E>.
+       * testsuite/20_util/expected/lwg3938.cc: New test.
+
+2023-06-01  Jonathan Wakely  <jwakely@redhat.com>
+
+       PR libstdc++/110060
+       * include/bits/stl_vector.h (_Vector_base::_M_invariant):
+       Remove.
+       (vector::size, vector::capacity): Remove calls to _M_invariant.
+       * include/bits/vector.tcc (vector::_M_fill_assign): Add
+       optimization hint to reallocating path.
+       (vector::_M_assign_aux(FwdIter, FwdIter, forward_iterator_tag)):
+       Likewise.
+       * testsuite/23_containers/vector/capacity/invariant.cc: Moved
+       to...
+       * testsuite/23_containers/vector/modifiers/assign/no_realloc.cc:
+       ...here. Check assign(FwdIter, FwdIter) too.
+       * testsuite/23_containers/vector/types/1.cc: Revert addition
+       of -Wno-stringop-overread option.
+
+2023-06-01  Jonathan Wakely  <jwakely@redhat.com>
+
+       * doc/xml/manual/evolution.xml: Document removal of implicit
+       allocator rebinding extensions in strict mode and for C++20.
+       * doc/html/*: Regenerate.
+
+2023-06-01  Jason Merrill  <jason@redhat.com>
+
+       * libsupc++/eh_personality.cc (PERSONALITY_FUNCTION): Don't check
+       handlers in the cleanup phase.
+
+2023-06-01  Matthias Kretz  <m.kretz@gsi.de>
+
+       PR libstdc++/110050
+       * include/experimental/bits/simd.h (__vectorized_sizeof): With
+       __have_neon_a32 only single-precision float works (in addition
+       to integers).
+
+2023-06-01  François Dumont  <fdumont@gcc.gnu.org>
+
+       * include/bits/stl_algo.h
+       (std::__search, std::search(_FwdIt1, _FwdIt1, _FwdIt2, _FwdIt2, _BinPred)): Move...
+       * include/bits/stl_algobase.h: ...here.
+       * include/std/functional: Replace <stl_algo.h> include by <stl_algobase.h>.
+       * include/parallel/algo.h (std::__parallel::search<_FIt1, _FIt2, _BinaryPred>)
+       (std::__parallel::__search_switch<_FIt1, _FIt2, _BinaryPred, _ItTag1, _ItTag2>):
+       Move...
+       * include/parallel/algobase.h: ...here.
+       * include/experimental/functional: Remove <bits/stl_algo.h> and <parallel/algorithm>
+       includes. Include <bits/stl_algobase.h>.
+
 2023-05-31  Jonathan Wakely  <jwakely@redhat.com>
 
        PR libstdc++/109818