Relax the overly-restrictive implementation of

  (T3) SUB{S}.W Rd, Rn, Rm, {shift}

in the case where Rn=SP, to allow |shift| values of 0,1,2,3
instead of just 0.  Fixes #354274.  Patch from dimitry@google.com.

git-svn-id: svn://svn.valgrind.org/vex/trunk@3257

diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
index e3e9f83f19fca9f530668db85df3ac26de22a668..6ce200603cee0cd4d8c90a9d674032c8b4a8b497 100644 (file)
--- a/VEX/priv/guest_arm_toIR.c
+++ b/VEX/priv/guest_arm_toIR.c
@@ -20576,10 +20576,10 @@ DisResult disInstr_THUMB_WRK (
           && rD != 15 && rN == 13 && imm5 <= 31 && how == 0) {
          valid = True;
       }
-      /* also allow "sub.w reg, sp, reg   w/ no shift
+      /* also allow "sub.w reg, sp, reg   lsl #N for N=0,1,2 or 3
          (T1) "SUB (SP minus register) */
       if (!valid && INSN0(8,5) == BITS4(1,1,0,1) // sub
-          && rD != 15 && rN == 13 && imm5 == 0 && how == 0) {
+          && rD != 15 && rN == 13 && imm5 <= 3 && how == 0) {
          valid = True;
       }
       if (valid) {