arm64: dts: qcom: sm8250: Use the header with DSI phy clock IDs

Use the header with DSI phy clock IDs to make code more readable.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-20-73b482a6dd02@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi
index 01a321d801af3389258abd54e60c39272c59fb7e..465fd6e954a347acf15ef3199afd8d1a198f95e8 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi
@@ -659,7 +659,8 @@
        qcom,dual-dsi-mode;
        qcom,sync-dual-dsi;
        /* DSI1 is slave, so use DSI0 clocks */
-       assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+       assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+                                <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
        status = "okay";
 };
 

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 68613ea7146c8882150f1b81dbc0f3384d3380ba..0425e14840c6a299aa49e82ef5010fc9ac090296 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
@@ -4861,8 +4862,10 @@
                                              "iface",
                                              "bus";
 
-                               assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
-                               assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+                               assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+                                                 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+                               assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+                                                        <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
 
                                operating-points-v2 = <&dsi_opp_table>;
                                power-domains = <&rpmhpd RPMHPD_MMCX>;
@@ -4953,8 +4956,10 @@
                                              "iface",
                                              "bus";
 
-                               assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
-                               assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
+                               assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
+                                                 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
+                               assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
+                                                        <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>;
 
                                operating-points-v2 = <&dsi_opp_table>;
                                power-domains = <&rpmhpd RPMHPD_MMCX>;
@@ -5011,10 +5016,10 @@
                        power-domains = <&rpmhpd RPMHPD_MMCX>;
                        required-opps = <&rpmhpd_opp_low_svs>;
                        clocks = <&rpmhcc RPMH_CXO_CLK>,
-                                <&mdss_dsi0_phy 0>,
-                                <&mdss_dsi0_phy 1>,
-                                <&mdss_dsi1_phy 0>,
-                                <&mdss_dsi1_phy 1>,
+                                <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+                                <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
+                                <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
+                                <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
                                 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
                                 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
                        clock-names = "bi_tcxo",