riscv: cpu: th1520: Support cache enabling/disabling in M mode only

These operations rely on a customized M-mode CSR, MHCR, which isn't
available when running in S mode.

Let's fallback to the generic weak stub when running in S mode to avoid
illegal accesses.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/cpu/th1520/cache.c b/arch/riscv/cpu/th1520/cache.c
index 08aa1f789fd6d356a6d1a9c945807ee4638080f3..b2fec229363b9d2f5024fa30af71fabb9de6f4e6 100644 (file)
--- a/arch/riscv/cpu/th1520/cache.c
+++ b/arch/riscv/cpu/th1520/cache.c
@@ -11,6 +11,7 @@
 #define  CSR_MHCR_IE           BIT(0)
 #define  CSR_MHCR_DE           BIT(1)
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
 void icache_enable(void)
 {
        csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_IE);
@@ -30,3 +31,4 @@ int dcache_status(void)
 {
        return (csr_read(CSR_MHCR) & CSR_MHCR_DE) != 0;
 }
+#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */