set_feature (FEATURE_AVXNECONVERT);
if (edx & bit_AVXVNNIINT16)
set_feature (FEATURE_AVXVNNIINT16);
+ if (eax & bit_SM3)
+ set_feature (FEATURE_SM3);
}
if (avx512_usable)
{
#define OPTION_MASK_ISA2_AMX_COMPLEX_SET \
(OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_COMPLEX)
#define OPTION_MASK_ISA2_AVXVNNIINT16_SET OPTION_MASK_ISA2_AVXVNNIINT16
+#define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3
/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2. */
#define OPTION_MASK_ISA2_RAOINT_UNSET OPTION_MASK_ISA2_RAOINT
#define OPTION_MASK_ISA2_AMX_COMPLEX_UNSET OPTION_MASK_ISA2_AMX_COMPLEX
#define OPTION_MASK_ISA2_AVXVNNIINT16_UNSET OPTION_MASK_ISA2_AVXVNNIINT16
+#define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
#define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
OPTION_MASK_ISA2_SSE_UNSET
#define OPTION_MASK_ISA2_AVX_UNSET \
- (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET)
+ (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET \
+ | OPTION_MASK_ISA2_SM3_UNSET)
#define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
#define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
#define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
}
return true;
+ case OPT_msm3:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SM3_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_SET;
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SM3_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_UNSET;
+ }
+ return true;
+
case OPT_mfma:
if (value)
{
FEATURE_RAOINT,
FEATURE_AMX_COMPLEX,
FEATURE_AVXVNNIINT16,
+ FEATURE_SM3,
CPU_FEATURE_MAX
};
P_NONE, "-mamx-complex")
ISA_NAMES_TABLE_ENTRY("avxvnniint16", FEATURE_AVXVNNIINT16,
P_NONE, "-mavxvnniint16")
+ ISA_NAMES_TABLE_ENTRY("sm3", FEATURE_SM3, P_NONE, "-msm3")
ISA_NAMES_TABLE_END
mwaitintrin.h avx512fp16intrin.h avx512fp16vlintrin.h
avxifmaintrin.h avxvnniint8intrin.h avxneconvertintrin.h
cmpccxaddintrin.h amxfp16intrin.h prfchiintrin.h
- raointintrin.h amxcomplexintrin.h avxvnniint16intrin.h"
+ raointintrin.h amxcomplexintrin.h avxvnniint16intrin.h
+ sm3intrin.h"
;;
ia64-*-*)
extra_headers=ia64intrin.h
/* Extended Features Sub-leaf (%eax == 7, %ecx == 1) */
/* %eax */
+#define bit_SM3 (1 << 1)
#define bit_RAOINT (1 << 3)
#define bit_AVXVNNI (1 << 4)
#define bit_AVX512BF16 (1 << 5)
# PREFETCHI builtins
DEF_FUNCTION_TYPE (VOID, PCVOID, INT)
DEF_FUNCTION_TYPE (VOID, PCVOID, INT, INT, INT)
+
+# SM3 builtins
+DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, INT)
BDESC (OPTION_MASK_ISA_SSE2, 0, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI)
BDESC (OPTION_MASK_ISA_SSE2, 0, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+/* SM3 */
+BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3msg1, "__builtin_ia32_vsm3msg1", IX86_BUILTIN_VSM3MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3msg2, "__builtin_ia32_vsm3msg2", IX86_BUILTIN_VSM3MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3rnds2, "__builtin_ia32_vsm3rnds2", IX86_BUILTIN_VSM3RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT)
+
/* AVX512VL. */
BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_USI_CONVERT)
BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_UHI_CONVERT)
def_or_undef (parse_in, "__AMX_COMPLEX__");
if (isa_flag2 & OPTION_MASK_ISA2_AVXVNNIINT16)
def_or_undef (parse_in, "__AVXVNNIINT16__");
+ if (isa_flag2 & OPTION_MASK_ISA2_SM3)
+ def_or_undef (parse_in, "__SM3__");
if (TARGET_IAMCU)
{
def_or_undef (parse_in, "__iamcu");
case V4SF_FTYPE_V4SF_V4SF_V4SI_INT:
case V8SF_FTYPE_V8SF_V8SF_V8SI_INT:
case V16SF_FTYPE_V16SF_V16SF_V16SI_INT:
+ case V4SI_FTYPE_V4SI_V4SI_V4SI_INT:
nargs = 4;
nargs_constant = 1;
break;
DEF_PTA(RAOINT)
DEF_PTA(AMX_COMPLEX)
DEF_PTA(AVXVNNIINT16)
+DEF_PTA(SM3)
{ "-mraoint", OPTION_MASK_ISA2_RAOINT },
{ "-mamx-complex", OPTION_MASK_ISA2_AMX_COMPLEX },
{ "-mavxvnniint16", OPTION_MASK_ISA2_AVXVNNIINT16 },
+ { "-msm3", OPTION_MASK_ISA2_SM3 }
};
static struct ix86_target_opts isa_opts[] =
{
IX86_ATTR_ISA ("raoint", OPT_mraoint),
IX86_ATTR_ISA ("amx-complex", OPT_mamx_complex),
IX86_ATTR_ISA ("avxvnniint16", OPT_mavxvnniint16),
+ IX86_ATTR_ISA ("sm3", OPT_msm3),
/* enum options */
IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
Target Mask(ISA2_AVXVNNIINT16) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and
AVXVNNIINT16 built-in functions and code generation.
+
+msm3
+Target Mask(ISA2_SM3) Var(ix86_isa_flags2) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and
+SM3 built-in functions and code generation.
#include <shaintrin.h>
+#include <sm3intrin.h>
+
#include <fmaintrin.h>
#include <f16cintrin.h>
--- /dev/null
+/* Copyright (C) 2023 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef _IMMINTRIN_H_INCLUDED
+#error "Never use <sm3intrin.h> directly; include <immintrin.h> instead."
+#endif
+
+#ifndef _SM3INTRIN_H_INCLUDED
+#define _SM3INTRIN_H_INCLUDED
+
+#ifndef __SM3__
+#pragma GCC push_options
+#pragma GCC target("sm3")
+#define __DISABLE_SM3__
+#endif /* __SM3__ */
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_sm3msg1_epi32 (__m128i __A, __m128i __B, __m128i __C)
+{
+ return (__m128i) __builtin_ia32_vsm3msg1 ((__v4si) __A, (__v4si) __B,
+ (__v4si) __C);
+}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_sm3msg2_epi32 (__m128i __A, __m128i __B, __m128i __C)
+{
+ return (__m128i) __builtin_ia32_vsm3msg2 ((__v4si) __A, (__v4si) __B,
+ (__v4si) __C);
+}
+
+#ifdef __OPTIMIZE__
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_sm3rnds2_epi32 (__m128i __A, __m128i __B, __m128i __C, const int __D)
+{
+ return (__m128i) __builtin_ia32_vsm3rnds2 ((__v4si) __A, (__v4si) __B,
+ (__v4si) __C, __D);
+}
+#else
+#define _mm_sm3rnds2_epi32(A, B, C, D) \
+ ((__m128i) __builtin_ia32_vsm3rnds2 ((__v4si) (A), (__v4si) (B), \
+ (__v4si) (C), (int) (D)))
+#endif
+
+#ifdef __DISABLE_SM3__
+#undef __DISABLE_SM3__
+#pragma GCC pop_options
+#endif /* __DISABLE_SM3__ */
+
+#endif /* _SM3INTRIN_H_INCLUDED */
UNSPEC_COMPLEX_FMUL
UNSPEC_COMPLEX_FCMUL
UNSPEC_COMPLEX_MASK
+
+ ;; For SM3 support
+ UNSPEC_SM3MSG1
+ UNSPEC_SM3MSG2
+ UNSPEC_SM3RNDS2
;; For AVX-VNNI-INT8 support
UNSPEC_VPDPBSSD
(set_attr "length_immediate" "1")
(set_attr "mode" "TI")])
+(define_insn "vsm3msg1"
+ [(set (match_operand:V4SI 0 "register_operand" "=x")
+ (unspec:V4SI
+ [(match_operand:V4SI 1 "register_operand" "0")
+ (match_operand:V4SI 2 "register_operand" "x")
+ (match_operand:V4SI 3 "vector_operand" "xBm")]
+ UNSPEC_SM3MSG1))]
+ "TARGET_SM3"
+ "vsm3msg1\t{%3, %2, %0|%0, %2, %3}"
+ [(set_attr "type" "other")
+ (set_attr "mode" "TI")])
+
+(define_insn "vsm3msg2"
+ [(set (match_operand:V4SI 0 "register_operand" "=x")
+ (unspec:V4SI
+ [(match_operand:V4SI 1 "register_operand" "0")
+ (match_operand:V4SI 2 "register_operand" "x")
+ (match_operand:V4SI 3 "vector_operand" "xBm")]
+ UNSPEC_SM3MSG2))]
+ "TARGET_SM3"
+ "vsm3msg2\t{%3, %2, %0|%0, %2, %3}"
+ [(set_attr "type" "other")
+ (set_attr "mode" "TI")])
+
+(define_insn "vsm3rnds2"
+ [(set (match_operand:V4SI 0 "register_operand" "=x")
+ (unspec:V4SI
+ [(match_operand:V4SI 1 "register_operand" "0")
+ (match_operand:V4SI 2 "register_operand" "x")
+ (match_operand:V4SI 3 "vector_operand" "xBm")
+ (match_operand:SI 4 "const_0_to_255_operand" "n")]
+ UNSPEC_SM3RNDS2))]
+ "TARGET_SM3"
+ "vsm3rnds2\t{%4, %3, %2, %0|%0, %2, %3, %4}"
+ [(set_attr "type" "other")
+ (set_attr "mode" "TI")
+ (set_attr "length_immediate" "1")])
+
(define_insn_and_split "avx512f_<castmode><avxsizesuffix>_<castmode>"
[(set (match_operand:AVX512MODE2P 0 "nonimmediate_operand" "=x,m")
(vec_concat:AVX512MODE2P
@itemx no-avxvnniint16
Enable/disable the generation of the AVXVNNIINT16 instructions.
+@cindex @code{target("sm3")} function attribute, x86
+@item sm3
+@itemx no-sm3
+Enable/disable the generation of the SM3 instructions.
+
@cindex @code{target("cld")} function attribute, x86
@item cld
@itemx no-cld
-mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk
-mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni
-mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16
--mprefetchi -mraoint -mamx-complex -mavxvnniint16
+-mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3
-mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops
-minline-stringops-dynamically -mstringop-strategy=@var{alg}
-mkl -mwidekl
@need 200
@opindex mavxvnniint16
@itemx -mavxvnniint16
+@need 200
+@opindex msm3
+@itemx -msm3
These switches enable the use of instructions in the MMX, SSE,
AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,
AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG,
ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE,
UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16,
AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT,
-AMX-COMPLEX, AVXVNNIINT16 or CLDEMOTE extended instruction sets. Each has a
+AMX-COMPLEX, AVXVNNIINT16, SM3 or CLDEMOTE extended instruction sets. Each has a
corresponding @option{-mno-} option to disable use of these instructions.
These extensions are also available as built-in functions: see
@item rdrand
Target supports x86 @code{rdrand} instruction.
+@item sm3
+Target supports the execution of @code{sm3} instructions.
+
@item sqrt_insn
Target has a square root instruction that the compiler can generate.
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16" } */
+/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3" } */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16" } */
+/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3" } */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
#define __builtin_ia32_cmpccxadd(A, B, C, D) __builtin_ia32_cmpccxadd(A, B, C, 1)
#define __builtin_ia32_cmpccxadd64(A, B, C, D) __builtin_ia32_cmpccxadd64(A, B, C, 1)
+/* sm3intrin.h */
+#define __builtin_ia32_vsm3rnds2(A, B, C, D) __builtin_ia32_vsm3rnds2 (A, B, C, 1)
+
#include <wmmintrin.h>
#include <immintrin.h>
#include <mm3dnow.h>
extern void test_raoint (void) __attribute__((__target__("raoint")));
extern void test_amx_complex (void) __attribute__((__target__("amx-complex")));
extern void test_avxvnniint16 (void) __attribute__((__target__("avxvnniint16")));
+extern void test_sm3 (void) __attribute__((__target__("sm3")));
extern void test_no_sgx (void) __attribute__((__target__("no-sgx")));
extern void test_no_avx5124fmaps(void) __attribute__((__target__("no-avx5124fmaps")));
extern void test_no_raoint (void) __attribute__((__target__("no-raoint")));
extern void test_no_amx_complex (void) __attribute__((__target__("no-amx-complex")));
extern void test_no_avxvnniint16 (void) __attribute__((__target__("no-avxvnniint16")));
+extern void test_no_sm3 (void) __attribute__((__target__("no-sm3")));
extern void test_arch_nocona (void) __attribute__((__target__("arch=nocona")));
extern void test_arch_core2 (void) __attribute__((__target__("arch=core2")));
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2 -msm3" } */
+/* { dg-final { scan-assembler "vsm3msg1\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "vsm3msg2\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "vsm3rnds2\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m128i x, y, z;
+
+void extern
+sm3_test (void)
+{
+ x = _mm_sm3msg1_epi32 (x, y, z);
+ x = _mm_sm3msg2_epi32 (x, y, z);
+ x = _mm_sm3rnds2_epi32 (x, y, z, 1);
+}
--- /dev/null
+#include <stdlib.h>
+#include "m128-check.h"
+
+static void sm3_test (void);
+
+static unsigned
+rol32 (unsigned w, int n)
+{
+ int count = n % 32;
+ return ((w << n) | (w >> (32 - n)));
+}
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+ sm3_test ();
+}
+
+int
+main ()
+{
+ /* Run SM3 test only if host has SM3 support. */
+ if (__builtin_cpu_supports ("sm3"))
+ {
+ do_test ();
+#ifdef DEBUG
+ printf ("PASSED\n");
+#endif
+ return 0;
+ }
+
+#ifdef DEBUG
+ printf ("SKIPPED\n");
+#endif
+ return 0;
+}
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-O2 -msm3" } */
+/* { dg-require-effective-target sm3 } */
+
+#include "sm3-check.h"
+#include <x86intrin.h>
+#include <immintrin.h>
+
+static unsigned
+p1 (unsigned w)
+{
+ return rol32 (w, 15) ^ rol32 (w, 23) ^ w;
+}
+
+static void
+compute_sm3msg1 (int *src0, int *src1, int *src2, int *res)
+{
+ unsigned w0, w1, w2, w3, w7, w8, w9, w10, w13, w14, w15;
+
+ w0 = src2[0];
+ w1 = src2[1];
+ w2 = src2[2];
+ w3 = src2[3];
+ w7 = src0[0];
+ w8 = src0[1];
+ w9 = src0[2];
+ w10 = src0[3];
+ w13 = src1[0];
+ w14 = src1[1];
+ w15 = src1[2];
+
+ res[0] = p1 (w7 ^ w0 ^ rol32 (w13, 15));
+ res[1] = p1 (w8 ^ w1 ^ rol32 (w14, 15));
+ res[2] = p1 (w9 ^ w2 ^ rol32 (w15, 15));
+ res[3] = p1 (w10 ^ w3);
+}
+
+static void
+sm3_test (void)
+{
+ union128i_d s1, s2, s3, res;
+ int res_ref[4];
+
+ s1.x = _mm_set_epi32 (111, 222, 333, 444);
+ s2.x = _mm_set_epi32 (555, 666, 777, 888);
+ s3.x = _mm_set_epi32 (999, 123, 456, 789);
+
+ res.x = _mm_sm3msg1_epi32 (s1.x, s2.x, s3.x);
+
+ compute_sm3msg1 (s1.a, s2.a, s3.a, res_ref);
+
+ if (check_union128i_d (res, res_ref))
+ abort ();
+}
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-O2 -msm3" } */
+/* { dg-require-effective-target sm3 } */
+
+#include "sm3-check.h"
+#include <x86intrin.h>
+#include <immintrin.h>
+
+static void
+compute_sm3msg2 (int *src0, int *src1, int *src2, int *res)
+{
+ unsigned wtmp0, wtmp1, wtmp2, wtmp3, w3, w4, w5, w6, w10, w11, w12, w13,
+ w16, w17, w18, w19;
+
+ wtmp0 = src0[0];
+ wtmp1 = src0[1];
+ wtmp2 = src0[2];
+ wtmp3 = src0[3];
+ w3 = src1[0];
+ w4 = src1[1];
+ w5 = src1[2];
+ w6 = src1[3];
+ w10 = src2[0];
+ w11 = src2[1];
+ w12 = src2[2];
+ w13 = src2[3];
+
+ w16 = rol32 (w3, 7) ^ w10 ^ wtmp0;
+ w17 = rol32 (w4, 7) ^ w11 ^ wtmp1;
+ w18 = rol32 (w5, 7) ^ w12 ^ wtmp2;
+ w19 = rol32 (w6, 7) ^ w13 ^ wtmp3;
+
+ w19 = w19 ^ rol32 (w16, 6) ^ rol32 (w16, 15) ^ rol32 (w16, 30) ;
+
+ res[0] = w16;
+ res[1] = w17;
+ res[2] = w18;
+ res[3] = w19;
+}
+
+static void
+sm3_test (void)
+{
+ union128i_d s1, s2, s3, res;
+ int res_ref[4];
+
+ s1.x = _mm_set_epi32 (111, 222, 333, 444);
+ s2.x = _mm_set_epi32 (555, 666, 777, 888);
+ s3.x = _mm_set_epi32 (999, 123, 456, 789);
+
+ res.x = _mm_sm3msg2_epi32 (s1.x, s2.x, s3.x);
+
+ compute_sm3msg2 (s1.a, s2.a, s3.a, res_ref);
+
+ if (check_union128i_d (res, res_ref))
+ abort ();
+}
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-O2 -msm3" } */
+/* { dg-require-effective-target sm3 } */
+
+#include "sm3-check.h"
+#include <x86intrin.h>
+#include <immintrin.h>
+
+static unsigned
+p0 (unsigned w)
+{
+ return (w ^ rol32 (w, 9) ^ rol32 (w, 17));
+}
+
+static unsigned
+ff (unsigned x, unsigned y, unsigned z, int round)
+{
+ if (round < 16)
+ return (x ^ y ^ z);
+ else
+ return ((x & y) | (x & z) | (y & z));
+}
+
+static unsigned
+gg (unsigned x, unsigned y, unsigned z, int round)
+{
+ if (round < 16)
+ return (x ^ y ^ z);
+ else
+ return ((x & y) | ((~x) & z));
+}
+
+static void
+compute_sm3rnds2 (int *src0, int *src1, int *src2, int imm, int *res)
+{
+ unsigned s1, s2, t1, t2, co;
+ unsigned w[6], a[3], b[3], c[3], d[3], e[3], f[3], g[3], h[3];
+ int round, i;
+
+ a[0] = src1[3];
+ b[0] = src1[2];
+ c[0] = src0[3];
+ d[0] = src0[2];
+ e[0] = src1[1];
+ f[0] = src1[0];
+ g[0] = src0[1];
+ h[0] = src0[0];
+ w[0] = src2[0];
+ w[1] = src2[1];
+ w[4] = src2[2];
+ w[5] = src2[3];
+
+ c[0] = rol32 (c[0], 9);
+ d[0] = rol32 (d[0], 9);
+ g[0] = rol32 (g[0], 19);
+ h[0] = rol32 (h[0], 19);
+
+ round = imm & 0x3e;
+ if (round < 16)
+ co = 0x79cc4519;
+ else
+ co = 0x7a879d8a;
+ co = rol32 (co, round);
+
+ for (i = 0; i < 2; i++)
+ {
+ s1 = rol32 ((rol32 (a[i], 12) + e[i] + co), 7);
+ s2 = s1 ^ rol32 (a[i], 12);
+ t1 = ff (a[i], b[i], c[i], round) + d[i] + s2 + (w[i] ^ w[i + 4]);
+ t2 = gg (e[i], f[i], g[i], round) + h[i] + s1 + w[i];
+ d[i + 1] = c[i];
+ c[i + 1] = rol32 (b[i], 9);
+ b[i + 1] = a[i];
+ a[i + 1] = t1;
+ h[i + 1] = g[i];
+ g[i + 1] = rol32 (f[i], 19);
+ f[i + 1] = e[i];
+ e[i + 1] = p0 (t2);
+ co = rol32 (co, 1);
+ }
+
+ res[3] = a[2];
+ res[2] = b[2];
+ res[1] = e[2];
+ res[0] = f[2];
+}
+
+static void
+sm3_test (void)
+{
+ union128i_d s1, s2, s3, res;
+ int res_ref[4];
+
+ s1.x = _mm_set_epi32 (111, 222, 333, 444);
+ s2.x = _mm_set_epi32 (555, 666, 777, 888);
+ s3.x = _mm_set_epi32 (999, 123, 456, 789);
+
+ res.x = _mm_sm3rnds2_epi32 (s1.x, s2.x, s3.x, 22);
+
+ compute_sm3rnds2 (s1.a, s2.a, s3.a, 22, res_ref);
+
+ if (check_union128i_d (res, res_ref))
+ abort ();
+}
popcntintrin.h gfniintrin.h and mm_malloc.h are usable
with -O -std=c89 -pedantic-errors. */
/* { dg-do compile } */
-/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16" } */
+/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3" } */
#include <x86intrin.h>
/* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16" } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>
#define __builtin_ia32_cmpccxadd(A, B, C, D) __builtin_ia32_cmpccxadd(A, B, C, 1)
#define __builtin_ia32_cmpccxadd64(A, B, C, D) __builtin_ia32_cmpccxadd64(A, B, C, 1)
+/* sm3intrin.h */
+#define __builtin_ia32_vsm3rnds2(A, B, C, D) __builtin_ia32_vsm3rnds2 (A, B, C, 1)
+
#include <x86intrin.h>
/* { dg-do compile } */
-/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16" } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>
test_2 (_mm_gf2p8affine_epi64_epi8, __m128i, __m128i, __m128i, 1)
test_2 (_mm256_gf2p8affine_epi64_epi8, __m256i, __m256i, __m256i, 1)
test_2 (_mm512_gf2p8affine_epi64_epi8, __m512i, __m512i, __m512i, 1)
+
+/* sm3intrin.h */
+test_3 (_mm_sm3rnds2_epi32, __m128i, __m128i, __m128i, __m128i, 1)
#ifndef DIFFERENT_PRAGMAS
-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16")
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3")
#endif
/* Following intrinsics require immediate arguments. They
/* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */
#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16")
+#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3")
#endif
#include <immintrin.h>
test_1 (_cvtss_sh, unsigned short, float, 1)
#ifdef __x86_64__
test_1 ( __bextri_u64, unsigned long long, unsigned long long, 1)
#endif
+
+/* sm3intrin.h */
+test_3 (_mm_sm3rnds2_epi32, __m128i, __m128i, __m128i, __m128i, 1)
#define __builtin_ia32_cmpccxadd(A, B, C, D) __builtin_ia32_cmpccxadd(A, B, C, 1)
#define __builtin_ia32_cmpccxadd64(A, B, C, D) __builtin_ia32_cmpccxadd64(A, B, C, 1)
-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16")
+/* sm3intrin.h */
+#define __builtin_ia32_vsm3rnds2(A, B, C, D) __builtin_ia32_vsm3rnds2 (A, B, C, 1)
+
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3")
#include <x86intrin.h>
} "-O0 -mavxvnniint16" ]
}
+# Return 1 if sm3 instructions can be compiled.
+proc check_effective_target_sm3 { } {
+ return [check_no_compiler_messages sm3 object {
+ typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+ typedef int __v4si __attribute__ ((__vector_size__ (16)));
+ __m128i
+ _mm_sm3msg1_epi32 (__m128i __A, __m128i __B, __m128i __C)
+ {
+ return (__m128i) __builtin_ia32_vsm3msg1 ((__v4si) __A,
+ (__v4si) __B,
+ (__v4si) __C);
+ }
+ } "-msm3" ]
+}
+
# Return 1 if sse instructions can be compiled.
proc check_effective_target_sse { } {
return [check_no_compiler_messages sse object {
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