* ppc-opc.c (RTO): Define.

	(powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
	entries to suit PPC440.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9085878e62c2bf7f34dfeaa13a8c0b0d56fe5dfb..dbf1775c8bfe853cf195f8f17c06269e93968827 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2005-04-19  Alan Modra  <amodra@bigpond.net.au>
+
+       * ppc-opc.c (RTO): Define.
+       (powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
+       entries to suit PPC440.
+
 2005-03-15  Jan Beulich  <jbeulich@novell.com>
 
        * i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 68f73d23bad083a69582295fda95a8bc91f90045..1fdd1b74fcb4f5400e96d2e17be20e42f54d0ddf 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -426,6 +426,7 @@ const struct powerpc_operand powerpc_operands[] =
 
   /* The RS field of the tlbwe instruction, which is optional.  */
 #define RSO RTQ + 1
+#define RTO RSO
   { 5, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 
   /* The SH field in an X or M form instruction.  */
@@ -4298,10 +4299,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mbar",    X(31,854),        X_MASK,         BOOKE,          { MO } },
 { "eieio",   X(31,854),        0xffffffff,     PPC,            { 0 } },
 
-{ "tlbsx",   XRC(31,914,0), X_MASK,    BOOKE,          { RA, RB } },
-{ "tlbsx",   XRC(31,914,0), X_MASK,    PPC403,         { RT, RA, RB } },
-{ "tlbsx.",  XRC(31,914,1), X_MASK,    BOOKE,          { RA, RB } },
-{ "tlbsx.",  XRC(31,914,1), X_MASK,    PPC403,         { RT, RA, RB } },
+{ "tlbsx",   XRC(31,914,0), X_MASK,    PPC403|BOOKE,   { RTO, RA, RB } },
+{ "tlbsx.",  XRC(31,914,1), X_MASK,    PPC403|BOOKE,   { RTO, RA, RB } },
 { "tlbsxe",  XRC(31,915,0), X_MASK,    BOOKE64,        { RA, RB } },
 { "tlbsxe.", XRC(31,915,1), X_MASK,    BOOKE64,        { RA, RB } },
 
@@ -4326,8 +4325,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "tlbrehi", XTLB(31,946,0), XTLB_MASK,        PPC403,         { RT, RA } },
 { "tlbrelo", XTLB(31,946,1), XTLB_MASK,        PPC403,         { RT, RA } },
-{ "tlbre",   X(31,946),        X_MASK,         BOOKE,          { 0 } },
-{ "tlbre",   X(31,946),        X_MASK,         PPC403,         { RS, RA, SH } },
+{ "tlbre",   X(31,946),        X_MASK,         PPC403|BOOKE,   { RSO, RAOPT, SHO } },
 
 { "sraiq",   XRC(31,952,0), X_MASK,    M601,           { RA, RS, SH } },
 { "sraiq.",  XRC(31,952,1), X_MASK,    M601,           { RA, RS, SH } },