arm64: dts: qcom: sm8750: Add IPCC, SMP2P, AOSS and ADSP

Add nodes for IPCC mailbox, SMP2P for ADSP, AOSS and the ADSP remoteproc
PAS loader (compatible with SM8550).

Reviewed-by: Melody Olvera <quic_molvera@quicinc.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250312-sm8750-audio-v3-1-40fbb3e53f95@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index a01ce74eebb3fa7b78acfefe421da7352063201a..f75f0723e39340d748b76c96816761831e06ceda 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -10,8 +10,10 @@
 #include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
 #include <dt-bindings/power/qcom,rpmhpd.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,gpr.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
 / {
@@ -516,6 +518,32 @@
                };
        };
 
+       smp2p-adsp {
+               compatible = "qcom,smp2p";
+
+               interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+                                            IPCC_MPROC_SIGNAL_SMP2P
+                                            IRQ_TYPE_EDGE_RISING>;
+
+               mboxes = <&ipcc IPCC_CLIENT_LPASS
+                               IPCC_MPROC_SIGNAL_SMP2P>;
+
+               qcom,smem = <443>, <429>;
+               qcom,local-pid = <0>;
+               qcom,remote-pid = <2>;
+
+               smp2p_adsp_out: master-kernel {
+                       qcom,entry-name = "master-kernel";
+                       #qcom,smem-state-cells = <1>;
+               };
+
+               smp2p_adsp_in: slave-kernel {
+                       qcom,entry-name = "slave-kernel";
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+       };
+
        soc: soc@0 {
                compatible = "simple-bus";
 
@@ -542,6 +570,17 @@
                        #power-domain-cells = <1>;
                };
 
+               ipcc: mailbox@406000 {
+                       compatible = "qcom,sm8750-ipcc", "qcom,ipcc";
+                       reg = <0x0 0x00406000 0x0 0x1000>;
+
+                       interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-controller;
+                       #interrupt-cells = <3>;
+
+                       #mbox-cells = <2>;
+               };
+
                gpi_dma2: dma-controller@800000 {
                        compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
                        reg = <0x0 0x00800000 0x0 0x60000>;
@@ -1988,6 +2027,94 @@
                        #hwlock-cells = <1>;
                };
 
+               remoteproc_adsp: remoteproc@6800000 {
+                       compatible = "qcom,sm8750-adsp-pas", "qcom,sm8550-adsp-pas";
+                       reg = <0x0 0x06800000 0x0 0x10000>;
+
+                       interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+                                             <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+                                             <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+                                             <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+                                             <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
+                                             <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "wdog",
+                                         "fatal",
+                                         "ready",
+                                         "handover",
+                                         "stop-ack",
+                                         "shutdown-ack";
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>;
+                       clock-names = "xo";
+
+                       interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+                       power-domains = <&rpmhpd RPMHPD_LCX>,
+                                       <&rpmhpd RPMHPD_LMX>;
+                       power-domain-names = "lcx",
+                                            "lmx";
+
+                       memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
+
+                       qcom,qmp = <&aoss_qmp>;
+
+                       qcom,smem-states = <&smp2p_adsp_out 0>;
+                       qcom,smem-state-names = "stop";
+
+                       status = "disabled";
+
+                       remoteproc_adsp_glink: glink-edge {
+                               interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+                                                            IPCC_MPROC_SIGNAL_GLINK_QMP
+                                                            IRQ_TYPE_EDGE_RISING>;
+                               mboxes = <&ipcc IPCC_CLIENT_LPASS
+                                               IPCC_MPROC_SIGNAL_GLINK_QMP>;
+                               qcom,remote-pid = <2>;
+                               label = "lpass";
+
+                               gpr {
+                                       compatible = "qcom,gpr";
+                                       qcom,glink-channels = "adsp_apps";
+                                       qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+                                       qcom,intents = <512 20>;
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       q6apm: service@1 {
+                                               compatible = "qcom,q6apm";
+                                               reg = <GPR_APM_MODULE_IID>;
+                                               #sound-dai-cells = <0>;
+                                               qcom,protection-domain = "avs/audio",
+                                                                        "msm/adsp/audio_pd";
+
+                                               q6apmbedai: bedais {
+                                                       compatible = "qcom,q6apm-lpass-dais";
+                                                       #sound-dai-cells = <1>;
+                                               };
+
+                                               q6apmdai: dais {
+                                                       compatible = "qcom,q6apm-dais";
+                                                       iommus = <&apps_smmu 0x1001 0x80>,
+                                                                <&apps_smmu 0x1041 0x20>;
+                                               };
+                                       };
+
+                                       q6prm: service@2 {
+                                               compatible = "qcom,q6prm";
+                                               reg = <GPR_PRM_MODULE_IID>;
+                                               qcom,protection-domain = "avs/audio",
+                                                                        "msm/adsp/audio_pd";
+
+                                               q6prmcc: clock-controller {
+                                                       compatible = "qcom,q6prm-lpass-clocks";
+                                                       #clock-cells = <2>;
+                                               };
+                                       };
+                               };
+                       };
+               };
+
                lpass_ag_noc: interconnect@7e40000 {
                        compatible = "qcom,sm8750-lpass-ag-noc";
                        reg = <0x0 0x07e40000 0x0 0xe080>;
@@ -2021,6 +2148,19 @@
                        interrupt-controller;
                };
 
+               aoss_qmp: power-management@c300000 {
+                       compatible = "qcom,sm8750-aoss-qmp", "qcom,aoss-qmp";
+                       reg = <0x0 0x0c300000 0x0 0x400>;
+
+                       interrupt-parent = <&ipcc>;
+                       interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
+                                                    IRQ_TYPE_EDGE_RISING>;
+
+                       mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+                       #clock-cells = <0>;
+               };
+
                sram@c3f0000 {
                        compatible = "qcom,rpmh-stats";
                        reg = <0x0 0x0c3f0000 0x0 0x400>;