const char * const *opp_pd_tbl;
unsigned int opp_pd_tbl_size;
const struct platform_clk_data *clk_tbl;
+ const char * const *opp_clk_tbl;
unsigned int clk_tbl_size;
const char * const *clk_rst_tbl;
unsigned int clk_rst_tbl_size;
{IRIS_HW_CLK, "vcodec0_core" },
};
+static const char * const sm8250_opp_clk_table[] = {
+ "vcodec0_core",
+ NULL,
+};
+
static struct tz_cp_config tz_cp_config_sm8250 = {
.cp_start = 0,
.cp_size = 0x25800000,
.opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table),
.clk_tbl = sm8250_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8250_clk_table),
+ .opp_clk_tbl = sm8250_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu-1.0/venus.mbn",
.opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table),
.clk_tbl = sc7280_clk_table,
.clk_tbl_size = ARRAY_SIZE(sc7280_clk_table),
+ .opp_clk_tbl = sc7280_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu20_p1.mbn",
{IRIS_HW_CLK, "vcodec0_core" },
};
+static const char * const sm8550_opp_clk_table[] = {
+ "vcodec0_core",
+ NULL,
+};
+
static struct ubwc_config_data ubwc_config_sm8550 = {
.max_channels = 8,
.mal_length = 32,
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8550_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
+ .opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu30_p4.mbn",
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8550_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
+ .opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu33_p4.mbn",
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8750_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8750_clk_table),
+ .opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu35_p4.mbn",
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8550_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
+ .opp_clk_tbl = sm8550_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.fwname = "qcom/vpu/vpu30_p4_s6.mbn",
{IRIS_HW_AHB_CLK, "vcodec_bus" },
};
+static const char * const sc7280_opp_clk_table[] = {
+ "vcodec_core",
+ NULL,
+};
+
#endif
}
core->power.clk_freq = freq;
- ret = dev_pm_opp_set_rate(core->dev, freq);
+ ret = iris_opp_set_rate(core->dev, freq);
mutex_unlock(&core->lock);
return ret;
static int iris_init_power_domains(struct iris_core *core)
{
- const struct platform_clk_data *clk_tbl;
- u32 clk_cnt, i;
int ret;
struct dev_pm_domain_attach_data iris_pd_data = {
.pd_flags = PD_FLAG_DEV_LINK_ON | PD_FLAG_REQUIRED_OPP,
};
+ struct dev_pm_opp_config iris_opp_clk_data = {
+ .clk_names = core->iris_platform_data->opp_clk_tbl,
+ .config_clks = dev_pm_opp_config_clks_simple,
+ };
+
ret = devm_pm_domain_attach_list(core->dev, &iris_pd_data, &core->pmdomain_tbl);
if (ret < 0)
return ret;
if (ret < 0)
return ret;
- clk_tbl = core->iris_platform_data->clk_tbl;
- clk_cnt = core->iris_platform_data->clk_tbl_size;
-
- for (i = 0; i < clk_cnt; i++) {
- if (clk_tbl[i].clk_type == IRIS_HW_CLK) {
- ret = devm_pm_opp_set_clkname(core->dev, clk_tbl[i].clk_name);
- if (ret)
- return ret;
- }
- }
+ ret = devm_pm_opp_set_config(core->dev, &iris_opp_clk_data);
+ if (ret)
+ return ret;
return devm_pm_opp_of_add_table(core->dev);
}
*/
#include <linux/clk.h>
+#include <linux/devfreq.h>
#include <linux/interconnect.h>
#include <linux/pm_domain.h>
#include <linux/pm_opp.h>
return icc_bulk_set_bw(core->icc_count, core->icc_tbl);
}
+int iris_opp_set_rate(struct device *dev, unsigned long freq)
+{
+ struct dev_pm_opp *opp __free(put_opp);
+
+ opp = devfreq_recommended_opp(dev, &freq, 0);
+ if (IS_ERR(opp))
+ return PTR_ERR(opp);
+
+ return dev_pm_opp_set_opp(dev, opp);
+}
+
int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev)
{
int ret;
- ret = dev_pm_opp_set_rate(core->dev, ULONG_MAX);
+ ret = iris_opp_set_rate(core->dev, ULONG_MAX);
if (ret)
return ret;
{
int ret;
- ret = dev_pm_opp_set_rate(core->dev, 0);
+ ret = iris_opp_set_rate(core->dev, 0);
if (ret)
return ret;
struct iris_core;
+int iris_opp_set_rate(struct device *dev, unsigned long freq);
int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev);
int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev);
int iris_unset_icc_bw(struct iris_core *core);
void iris_vpu_power_off(struct iris_core *core)
{
- dev_pm_opp_set_rate(core->dev, 0);
+ iris_opp_set_rate(core->dev, 0);
core->iris_platform_data->vpu_ops->power_off_hw(core);
core->iris_platform_data->vpu_ops->power_off_controller(core);
iris_unset_icc_bw(core);
freq = core->power.clk_freq ? core->power.clk_freq :
(u32)ULONG_MAX;
- dev_pm_opp_set_rate(core->dev, freq);
+ iris_opp_set_rate(core->dev, freq);
core->iris_platform_data->set_preset_registers(core);