irqchip/qcom-pdc: Use FIELD_GET() to extract bank index and bit position

The IRQ_ENABLE_BANK register is a bank of 32-bit words where each bit
represents one PDC pin. The bank index and bit position within the bank
are encoded in the flat pin number as bits [31:5] and [4:0] respectively.

Replace the open-coded division and modulo with FIELD_GET() and GENMASK()
to make the bit extraction self-documenting and consistent with the
FIELD_PREP() style already used in the PDC_VERSION() macro.

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://patch.msgid.link/20260527095426.2324504-5-mukesh.ojha@oss.qualcomm.com

diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index 08eec00a9cfe75b73a45864931dbc8b9267a81ff..2014dbb0bc43a44c56ef87c824fefb5b3612580e 100644 (file)
--- a/drivers/irqchip/qcom-pdc.c
+++ b/drivers/irqchip/qcom-pdc.c
@@ -27,6 +27,8 @@
 /* Valid only on HW version < 3.2 */
 #define IRQ_ENABLE_BANK                0x10
 #define IRQ_ENABLE_BANK_MAX    (IRQ_ENABLE_BANK + BITS_TO_BYTES(PDC_MAX_GPIO_IRQS))
+#define IRQ_ENABLE_BANK_INDEX_MASK     GENMASK(31, 5)
+#define IRQ_ENABLE_BANK_BIT_MASK       GENMASK(4, 0)
 #define IRQ_i_CFG              0x110
 
 /* Valid only on HW version >= 3.2 */
@@ -109,8 +111,8 @@ static void pdc_enable_intr_bank(int pin_out, bool on)
        unsigned long enable;
        u32 index, mask;
 
-       index = pin_out / 32;
-       mask = pin_out % 32;
+       index = FIELD_GET(IRQ_ENABLE_BANK_INDEX_MASK, pin_out);
+       mask = FIELD_GET(IRQ_ENABLE_BANK_BIT_MASK, pin_out);
 
        enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
        __assign_bit(mask, &enable, on);