Support the PLI instruction (icache preload hint) in ARM mode, so

as to make self-hosting on ARM work.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2023

diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
index b2e30d4375c68016579f83bed5214ca108f61cd3..bc588c6289dab7d4f75d83ce091536547ab720a3 100644 (file)
--- a/VEX/priv/guest_arm_toIR.c
+++ b/VEX/priv/guest_arm_toIR.c
@@ -11758,6 +11758,16 @@ static Bool decode_NV_instruction ( /*MOD*/DisResult* dres, UInt insn )
       /* fall through */
    }
 
+   /* ------------------------ pli ------------------------ */
+   if (BITS8(0,1,0,0, 0, 1,0,1) == (INSN(27,20) & BITS8(1,1,1,1,0,1,1,1))
+       && BITS4(1,1,1,1) == INSN(15,12)) {
+      UInt rN    = INSN(19,16);
+      UInt imm12 = INSN(11,0);
+      UInt bU    = INSN(23,23);
+      DIP("pli [r%u, #%c%u]\n", rN, bU ? '+' : '-', imm12);
+      return True;
+   }
+
    /* --------------------- Interworking branches --------------------- */
 
    // BLX (1), viz, unconditional branch and link to R15+simm24