clk: renesas: rzv2h: Deassert reset on assert timeout

If the assert() fails due to timeout error, set the reset register bit
back to deasserted state. This change is needed especially for handling
assert error in suspend() callback that expect the device to be in
operational state in case of failure.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260108123433.104464-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 3f6299b9fec051a7d384581f909b58e04c877666..1db92284025e25b948f807e401a8fc8855912263 100644 (file)
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -1352,6 +1352,7 @@ static int __rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
        u32 mask = BIT(priv->resets[id].reset_bit);
        u8 monbit = priv->resets[id].mon_bit;
        u32 value = mask << 16;
+       u32 mon;
        int ret;
 
        dev_dbg(rcdev->dev, "%s id:%ld offset:0x%x\n",
@@ -1364,10 +1365,10 @@ static int __rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
        reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
        mask = BIT(monbit);
 
-       ret = readl_poll_timeout_atomic(priv->base + reg, value,
-                                       assert == !!(value & mask), 10, 200);
-       if (ret && !assert) {
-               value = mask << 16;
+       ret = readl_poll_timeout_atomic(priv->base + reg, mon,
+                                       assert == !!(mon & mask), 10, 200);
+       if (ret) {
+               value ^= mask;
                writel(value, priv->base + GET_RST_OFFSET(priv->resets[id].reset_index));
        }