struct st_lsm6dsx_event_src {
struct st_lsm6dsx_reg value;
+ u8 enable_mask;
struct st_lsm6dsx_reg status;
u8 status_x_mask;
u8 status_y_mask;
struct {
struct st_lsm6dsx_reg irq1;
struct st_lsm6dsx_reg irq2;
- struct st_lsm6dsx_reg irq1_func;
- struct st_lsm6dsx_reg irq2_func;
+ u8 irq1_func;
+ u8 irq2_func;
struct st_lsm6dsx_reg lir;
struct st_lsm6dsx_reg clear_on_read;
struct st_lsm6dsx_reg hla;
u8 ts_sip;
u8 sip;
- const struct st_lsm6dsx_reg *irq_routing;
+ u8 irq_routing;
u8 event_threshold;
u8 enable_event;
.addr = 0x58,
.mask = BIT(0),
},
- .irq1_func = {
- .addr = 0x5e,
- .mask = BIT(5),
- },
- .irq2_func = {
- .addr = 0x5f,
- .mask = BIT(5),
- },
+ .irq1_func = 0x5e,
+ .irq2_func = 0x5f,
.hla = {
.addr = 0x12,
.mask = BIT(5),
.addr = 0x5b,
.mask = GENMASK(5, 0),
},
+ .enable_mask = BIT(5),
.status = {
.addr = 0x1b,
.mask = BIT(3),
.addr = 0x58,
.mask = BIT(0),
},
- .irq1_func = {
- .addr = 0x5e,
- .mask = BIT(5),
- },
- .irq2_func = {
- .addr = 0x5f,
- .mask = BIT(5),
- },
+ .irq1_func = 0x5e,
+ .irq2_func = 0x5f,
.hla = {
.addr = 0x12,
.mask = BIT(5),
.addr = 0x5b,
.mask = GENMASK(5, 0),
},
+ .enable_mask = BIT(5),
.status = {
.addr = 0x1b,
.mask = BIT(3),
.addr = 0x58,
.mask = BIT(0),
},
- .irq1_func = {
- .addr = 0x5e,
- .mask = BIT(5),
- },
- .irq2_func = {
- .addr = 0x5f,
- .mask = BIT(5),
- },
+ .irq1_func = 0x5e,
+ .irq2_func = 0x5f,
.hla = {
.addr = 0x12,
.mask = BIT(5),
.addr = 0x5b,
.mask = GENMASK(5, 0),
},
+ .enable_mask = BIT(5),
.status = {
.addr = 0x1b,
.mask = BIT(3),
.addr = 0x56,
.mask = BIT(6),
},
- .irq1_func = {
- .addr = 0x5e,
- .mask = BIT(5),
- },
- .irq2_func = {
- .addr = 0x5f,
- .mask = BIT(5),
- },
+ .irq1_func = 0x5e,
+ .irq2_func = 0x5f,
.hla = {
.addr = 0x12,
.mask = BIT(5),
.addr = 0x5b,
.mask = GENMASK(5, 0),
},
+ .enable_mask = BIT(5),
.status = {
.addr = 0x1b,
.mask = BIT(3),
.addr = 0x56,
.mask = BIT(6),
},
- .irq1_func = {
- .addr = 0x5e,
- .mask = BIT(5),
- },
- .irq2_func = {
- .addr = 0x5f,
- .mask = BIT(5),
- },
+ .irq1_func = 0x5e,
+ .irq2_func = 0x5f,
.hla = {
.addr = 0x12,
.mask = BIT(5),
.addr = 0x5b,
.mask = GENMASK(5, 0),
},
+ .enable_mask = BIT(5),
.status = {
.addr = 0x1b,
.mask = BIT(3),
.addr = 0x56,
.mask = BIT(0),
},
- .irq1_func = {
- .addr = 0x5e,
- .mask = BIT(5),
- },
- .irq2_func = {
- .addr = 0x5f,
- .mask = BIT(5),
- },
+ .irq1_func = 0x5e,
+ .irq2_func = 0x5f,
.hla = {
.addr = 0x03,
.mask = BIT(4),
.addr = 0x5b,
.mask = GENMASK(5, 0),
},
+ .enable_mask = BIT(5),
.status = {
.addr = 0x45,
.mask = BIT(3),
static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, bool state)
{
const struct st_lsm6dsx_reg *reg;
+ const struct st_lsm6dsx_event_src *src;
unsigned int data;
int err;
- if (!hw->settings->irq_config.irq1_func.addr)
+ if (!hw->irq_routing)
return -ENOTSUPP;
reg = &hw->settings->event_settings.enable_reg;
}
/* Enable wakeup interrupt */
- data = ST_LSM6DSX_SHIFT_VAL(state, hw->irq_routing->mask);
- return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing->addr,
- hw->irq_routing->mask, data);
+ src = &hw->settings->event_settings.sources[ST_LSM6DSX_EVENT_WAKEUP];
+ data = ST_LSM6DSX_SHIFT_VAL(state, src->enable_mask);
+ return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing,
+ src->enable_mask, data);
}
static int st_lsm6dsx_read_event(struct iio_dev *iio_dev,
switch (drdy_pin) {
case 1:
- hw->irq_routing = &hw->settings->irq_config.irq1_func;
+ hw->irq_routing = hw->settings->irq_config.irq1_func;
*drdy_reg = &hw->settings->irq_config.irq1;
break;
case 2:
- hw->irq_routing = &hw->settings->irq_config.irq2_func;
+ hw->irq_routing = hw->settings->irq_config.irq2_func;
*drdy_reg = &hw->settings->irq_config.irq2;
break;
default: