]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
clk: qcom: Constify list of critical CBCR registers
authorKrzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Tue, 31 Mar 2026 09:17:23 +0000 (11:17 +0200)
committerBjorn Andersson <andersson@kernel.org>
Sun, 5 Apr 2026 19:34:36 +0000 (14:34 -0500)
The static array 'xxx_critical_cbcrs' contains probe match-like data and
is not modified: neither by the driver defining it nor by common.c code
using it.

Make it const for code safety and code readability.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260331091721.61613-4-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
32 files changed:
drivers/clk/qcom/cambistmclkcc-kaanapali.c
drivers/clk/qcom/cambistmclkcc-sm8750.c
drivers/clk/qcom/camcc-kaanapali.c
drivers/clk/qcom/camcc-milos.c
drivers/clk/qcom/camcc-sc8180x.c
drivers/clk/qcom/camcc-sm8450.c
drivers/clk/qcom/camcc-sm8550.c
drivers/clk/qcom/camcc-sm8650.c
drivers/clk/qcom/camcc-sm8750.c
drivers/clk/qcom/camcc-x1e80100.c
drivers/clk/qcom/common.h
drivers/clk/qcom/dispcc-eliza.c
drivers/clk/qcom/dispcc-glymur.c
drivers/clk/qcom/dispcc-kaanapali.c
drivers/clk/qcom/dispcc-milos.c
drivers/clk/qcom/dispcc-qcs615.c
drivers/clk/qcom/gcc-eliza.c
drivers/clk/qcom/gcc-glymur.c
drivers/clk/qcom/gcc-kaanapali.c
drivers/clk/qcom/gcc-milos.c
drivers/clk/qcom/gcc-sc8180x.c
drivers/clk/qcom/gpucc-glymur.c
drivers/clk/qcom/gpucc-kaanapali.c
drivers/clk/qcom/gpucc-milos.c
drivers/clk/qcom/gpucc-qcs615.c
drivers/clk/qcom/videocc-glymur.c
drivers/clk/qcom/videocc-kaanapali.c
drivers/clk/qcom/videocc-milos.c
drivers/clk/qcom/videocc-qcs615.c
drivers/clk/qcom/videocc-sm8450.c
drivers/clk/qcom/videocc-sm8550.c
drivers/clk/qcom/videocc-sm8750.c

index 77adb453ab2192151552241ee270893c385fa46e..6028d8f6959c9e6b4d4116ad28ed038a488ee764 100644 (file)
@@ -383,7 +383,7 @@ static struct clk_alpha_pll *cam_bist_mclk_cc_kaanapali_plls[] = {
        &cam_bist_mclk_cc_pll0,
 };
 
-static u32 cam_bist_mclk_cc_kaanapali_critical_cbcrs[] = {
+static const u32 cam_bist_mclk_cc_kaanapali_critical_cbcrs[] = {
        0x40e0, /* CAM_BIST_MCLK_CC_SLEEP_CLK */
 };
 
index f0d7e3b7c5320a5b975262f1518a1d8fdb9d9a37..5df12aced4a552084359e34665845d9b81df2295 100644 (file)
@@ -402,7 +402,7 @@ static struct clk_alpha_pll *cam_bist_mclk_cc_sm8750_plls[] = {
        &cam_bist_mclk_cc_pll0,
 };
 
-static u32 cam_bist_mclk_cc_sm8750_critical_cbcrs[] = {
+static const u32 cam_bist_mclk_cc_sm8750_critical_cbcrs[] = {
        0x40f8, /* CAM_BIST_MCLK_CC_SLEEP_CLK */
 };
 
index acf5f476955b1805b62c334074b3cfffab1bd209..af5486418492e46d7ee79b2456fd76a6082f2369 100644 (file)
@@ -2600,7 +2600,7 @@ static struct clk_alpha_pll *cam_cc_kaanapali_plls[] = {
        &cam_cc_pll7,
 };
 
-static u32 cam_cc_kaanapali_critical_cbcrs[] = {
+static const u32 cam_cc_kaanapali_critical_cbcrs[] = {
        0x21398, /* CAM_CC_DRV_AHB_CLK */
        0x21390, /* CAM_CC_DRV_XO_CLK */
        0x21364, /* CAM_CC_GDSC_CLK */
index 556c3c33c10620f8c776f19d42dddc429dba8c2c..409d47098c109e69ae5d14904172db01eecf9b1a 100644 (file)
@@ -2104,7 +2104,7 @@ static struct clk_alpha_pll *cam_cc_milos_plls[] = {
        &cam_cc_pll6,
 };
 
-static u32 cam_cc_milos_critical_cbcrs[] = {
+static const u32 cam_cc_milos_critical_cbcrs[] = {
        0x25038, /* CAM_CC_GDSC_CLK */
        0x2505c, /* CAM_CC_SLEEP_CLK */
 };
index bd06d271928e47f4108b903b4a0c10dcf583ae6a..016f37d08468598e63081da6502e583fd5313fb9 100644 (file)
@@ -2829,7 +2829,7 @@ static struct clk_alpha_pll *cam_cc_sc8180x_plls[] = {
        &cam_cc_pll6,
 };
 
-static u32 cam_cc_sc8180x_critical_cbcrs[] = {
+static const u32 cam_cc_sc8180x_critical_cbcrs[] = {
        0xc1e4, /* CAM_CC_GDSC_CLK */
        0xc200, /* CAM_CC_SLEEP_CLK */
 };
index 430b436a673eedc628ba0f9fd702f5b990f476c0..1891262a559bfddc6233ddb1d5cbc12ca45540a0 100644 (file)
@@ -2915,7 +2915,7 @@ static struct clk_alpha_pll *cam_cc_sm8450_plls[] = {
        &cam_cc_pll8,
 };
 
-static u32 cam_cc_sm8450_critical_cbcrs[] = {
+static const u32 cam_cc_sm8450_critical_cbcrs[] = {
        0x1320c, /* CAM_CC_GDSC_CLK */
 };
 
index 8c42ae7544aa2b0d662945619f56ab7a975b4622..34d53e2ffad7470c0eaa2e61ab6e513862275a98 100644 (file)
@@ -3517,7 +3517,7 @@ static struct clk_alpha_pll *cam_cc_sm8550_plls[] = {
        &cam_cc_pll12,
 };
 
-static u32 cam_cc_sm8550_critical_cbcrs[] = {
+static const u32 cam_cc_sm8550_critical_cbcrs[] = {
        0x1419c, /* CAM_CC_GDSC_CLK */
        0x142cc, /* CAM_CC_SLEEP_CLK */
 };
index c0055fb08f62cc8e93e8715be2dde6c1b783ec67..9dea43e74cb6c64c352e81e2b38df0fac1c5109a 100644 (file)
@@ -3533,7 +3533,7 @@ static struct clk_alpha_pll *cam_cc_sm8650_plls[] = {
        &cam_cc_pll10,
 };
 
-static u32 cam_cc_sm8650_critical_cbcrs[] = {
+static const u32 cam_cc_sm8650_critical_cbcrs[] = {
        0x132ec, /* CAM_CC_GDSC_CLK */
        0x13308, /* CAM_CC_SLEEP_CLK */
        0x13314, /* CAM_CC_DRV_XO_CLK */
index 9b6d499812678468ae072636ffe0356f23618f6e..6618b074c90ea5fb64ee96f4df01cc8b11204cb6 100644 (file)
@@ -2651,7 +2651,7 @@ static struct clk_alpha_pll *cam_cc_sm8750_plls[] = {
        &cam_cc_pll6,
 };
 
-static u32 cam_cc_sm8750_critical_cbcrs[] = {
+static const u32 cam_cc_sm8750_critical_cbcrs[] = {
        0x113c4, /* CAM_CC_DRV_AHB_CLK */
        0x113c0, /* CAM_CC_DRV_XO_CLK */
        0x1137c, /* CAM_CC_GDSC_CLK */
index 38742053312589db96a8bd1618065df656b41d77..81f579ff6993349f4993fd2de14605379711f90a 100644 (file)
@@ -2434,7 +2434,7 @@ static struct clk_alpha_pll *cam_cc_x1e80100_plls[] = {
        &cam_cc_pll8,
 };
 
-static u32 cam_cc_x1e80100_critical_cbcrs[] = {
+static const u32 cam_cc_x1e80100_critical_cbcrs[] = {
        0x13a9c, /* CAM_CC_GDSC_CLK */
        0x13ab8, /* CAM_CC_SLEEP_CLK */
 };
index 69c4b21333e5967a16c0a1cc47a2b45b81a6fc06..6f2406f8839e8f432ef34ce32c930cf045f6ae7a 100644 (file)
@@ -28,7 +28,7 @@ struct qcom_icc_hws_data {
 struct qcom_cc_driver_data {
        struct clk_alpha_pll **alpha_plls;
        size_t num_alpha_plls;
-       u32 *clk_cbcrs;
+       const u32 *clk_cbcrs;
        size_t num_clk_cbcrs;
        const struct clk_rcg_dfs_data *dfs_rcgs;
        size_t num_dfs_rcgs;
index 60de3c743621efb62e17faa96c6a1625fa4ab281..479f26e0dde2937f0a623bfebcd315ec81cb6b9a 100644 (file)
@@ -2063,7 +2063,7 @@ static struct clk_alpha_pll *disp_cc_eliza_plls[] = {
        &disp_cc_pll2,
 };
 
-static u32 disp_cc_eliza_critical_cbcrs[] = {
+static const u32 disp_cc_eliza_critical_cbcrs[] = {
        0xe07c, /* DISP_CC_SLEEP_CLK */
        0xe05c, /* DISP_CC_XO_CLK */
        0xc00c, /* DISP_CC_MDSS_RSCC_AHB_CLK */
index aae60291b55e678e992f05a0f96cf392bce74494..c4bb328d432f2649a1d506db86bebc941de2ccc4 100644 (file)
@@ -1921,7 +1921,7 @@ static struct clk_alpha_pll *disp_cc_glymur_plls[] = {
        &disp_cc_pll1,
 };
 
-static u32 disp_cc_glymur_critical_cbcrs[] = {
+static const u32 disp_cc_glymur_critical_cbcrs[] = {
        0xe07c, /* DISP_CC_SLEEP_CLK */
        0xe05c, /* DISP_CC_XO_CLK */
 };
index ffdb4de3a33e776da3f7024692a26623bfce1bc8..42912c617c314c79799e0fbe777b6b4ba9f6f391 100644 (file)
@@ -1886,7 +1886,7 @@ static struct clk_alpha_pll *disp_cc_kaanapali_plls[] = {
        &disp_cc_pll2,
 };
 
-static u32 disp_cc_kaanapali_critical_cbcrs[] = {
+static const u32 disp_cc_kaanapali_critical_cbcrs[] = {
        0xe064, /* DISP_CC_SLEEP_CLK */
        0xe05c, /* DISP_CC_XO_CLK */
        0xc00c, /* DISP_CC_MDSS_RSCC_AHB_CLK */
index 17ff10cb2f6b91ce0d518b4a132e406afec8b89f..dfffb6d14b0ea8715a4d4f9ce2ab32431168a0e3 100644 (file)
@@ -906,7 +906,7 @@ static struct clk_alpha_pll *disp_cc_milos_plls[] = {
        &disp_cc_pll0,
 };
 
-static u32 disp_cc_milos_critical_cbcrs[] = {
+static const u32 disp_cc_milos_critical_cbcrs[] = {
        0xe06c, /* DISP_CC_SLEEP_CLK */
        0xe04c, /* DISP_CC_XO_CLK */
 };
index 21974e2574f58a12b266b7bf2bb39c331cc5c871..637698e6dc2bac94e604f915c44afe2668b780fc 100644 (file)
@@ -739,7 +739,7 @@ static struct clk_alpha_pll *disp_cc_qcs615_plls[] = {
        &disp_cc_pll0,
 };
 
-static u32 disp_cc_qcs615_critical_cbcrs[] = {
+static const u32 disp_cc_qcs615_critical_cbcrs[] = {
        0x6054, /* DISP_CC_XO_CLK */
 };
 
index dc8ccd2d27d0a035a84ab93b94e717ff6edae556..24c3aae0810f326671d2dd756be59abea250e27a 100644 (file)
@@ -3005,7 +3005,7 @@ static const struct qcom_reset_map gcc_eliza_resets[] = {
        [GCC_VIDEO_BCR] = { 0x32000 },
 };
 
-static u32 gcc_eliza_critical_cbcrs[] = {
+static const u32 gcc_eliza_critical_cbcrs[] = {
        0xa0004, /* GCC_CAM_BIST_MCLK_AHB_CLK */
        0x26004, /* GCC_CAMERA_AHB_CLK */
        0x26034, /* GCC_CAMERA_XO_CLK */
index 7a199e1bd49312e3655f1a672c232b9ef6ab59cb..2736465efdea9b3cf9ec945107d4b002e123b59f 100644 (file)
@@ -8538,7 +8538,7 @@ static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
        DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),
 };
 
-static u32 gcc_glymur_critical_cbcrs[] = {
+static const u32 gcc_glymur_critical_cbcrs[] = {
        0x26004, /* GCC_CAMERA_AHB_CLK */
        0x26040, /* GCC_CAMERA_XO_CLK */
        0x27004, /* GCC_DISP_AHB_CLK */
index 44275bac095ecb4a50db2d07189ffbb8aae12184..6e628b51f38c3acc147fc09c2cb7564e9f2ebe03 100644 (file)
@@ -3457,7 +3457,7 @@ static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
        DEFINE_RCG_DFS(gcc_qupv3_wrap4_s4_clk_src),
 };
 
-static u32 gcc_kaanapali_critical_cbcrs[] = {
+static const u32 gcc_kaanapali_critical_cbcrs[] = {
        0xa0004, /* GCC_CAM_BIST_MCLK_AHB_CLK */
        0x26004, /* GCC_CAMERA_AHB_CLK */
        0x2603c, /* GCC_CAMERA_XO_CLK */
index 3438fb9039ee6ab714edf6c1680f464503bac758..67d0eee8ef351418867ab3f8ce6165dc8773c34d 100644 (file)
@@ -3152,7 +3152,7 @@ static struct gdsc *gcc_milos_gdscs[] = {
        [USB3_PHY_GDSC] = &usb3_phy_gdsc,
 };
 
-static u32 gcc_milos_critical_cbcrs[] = {
+static const u32 gcc_milos_critical_cbcrs[] = {
        0x26004, /* GCC_CAMERA_AHB_CLK */
        0x26018, /* GCC_CAMERA_HF_XO_CLK */
        0x2601c, /* GCC_CAMERA_SF_XO_CLK */
index 35c2e9d555b865ccfcdf0e373741a59ddea7bdaa..e6b7f1a5dcef25b54153543c87dfe0c2ee01d5f5 100644 (file)
@@ -4647,7 +4647,7 @@ static struct gdsc *gcc_sc8180x_gdscs[] = {
        [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
 };
 
-static u32 gcc_sc8180x_critical_cbcrs[] = {
+static const u32 gcc_sc8180x_critical_cbcrs[] = {
        0xb004,  /* GCC_VIDEO_AHB_CLK */
        0xb008,  /* GCC_CAMERA_AHB_CLK */
        0xb00c,  /* GCC_DISP_AHB_CLK */
index 824b4e09c3f93dd87ba13f47933fbb92a46b4a95..54cc3127718af22c210cc51c13bfddf8e8c748c7 100644 (file)
@@ -560,7 +560,7 @@ static struct clk_alpha_pll *gpu_cc_glymur_plls[] = {
        &gpu_cc_pll0,
 };
 
-static u32 gpu_cc_glymur_critical_cbcrs[] = {
+static const u32 gpu_cc_glymur_critical_cbcrs[] = {
        0x93a4, /* GPU_CC_CB_CLK */
        0x9008, /* GPU_CC_CXO_AON_CLK */
        0x9004, /* GPU_CC_RSCC_XO_AON_CLK */
index 94f0feb254b39d83cbd38280ece1f5df25119fc0..7f6013b348ad4864cead0eb583571429dd848da7 100644 (file)
@@ -423,7 +423,7 @@ static struct clk_alpha_pll *gpu_cc_kaanapali_plls[] = {
        &gpu_cc_pll0,
 };
 
-static u32 gpu_cc_kaanapali_critical_cbcrs[] = {
+static const u32 gpu_cc_kaanapali_critical_cbcrs[] = {
        0x9008, /* GPU_CC_CXO_AON_CLK */
        0x93e8, /* GPU_CC_RSCC_HUB_AON_CLK */
        0x9004, /* GPU_CC_RSCC_XO_AON_CLK */
index 7a8a3917db9b6b3f6a8ba66b0a1ae7f2905aad92..1448d95cb1dc3cff6d7a0ca00137d9e975ef29d3 100644 (file)
@@ -500,7 +500,7 @@ static struct clk_alpha_pll *gpu_cc_milos_plls[] = {
        &gpu_cc_pll0,
 };
 
-static u32 gpu_cc_milos_critical_cbcrs[] = {
+static const u32 gpu_cc_milos_critical_cbcrs[] = {
        0x93a4, /* GPU_CC_CB_CLK */
        0x9008, /* GPU_CC_CXO_AON_CLK */
        0x9010, /* GPU_CC_DEMET_CLK */
index 8233136db4d8d148db22a9a129a0feec3e9c3477..91919cdb75aecb88ef67c2472f4e16808f48e106 100644 (file)
@@ -459,7 +459,7 @@ static struct clk_alpha_pll *gpu_cc_qcs615_plls[] = {
        &gpu_cc_pll1,
 };
 
-static u32 gpu_cc_qcs615_critical_cbcrs[] = {
+static const u32 gpu_cc_qcs615_critical_cbcrs[] = {
        0x1078, /* GPU_CC_AHB_CLK */
 };
 
index 4f1ad0db30e56a515575e35d26bfedf504d9fbf1..bbf13f4ba82dba7572edf0a4effa86c580c5de9d 100644 (file)
@@ -467,7 +467,7 @@ static struct clk_alpha_pll *video_cc_glymur_plls[] = {
        &video_cc_pll0,
 };
 
-static u32 video_cc_glymur_critical_cbcrs[] = {
+static const u32 video_cc_glymur_critical_cbcrs[] = {
        0x80e0, /* VIDEO_CC_AHB_CLK */
        0x8138, /* VIDEO_CC_SLEEP_CLK */
        0x8110, /* VIDEO_CC_XO_CLK */
index b060ee34e8a43cbe20791b37cf5e79742857f273..b29e3da465e5df436bdb4b0ec65648872a3f3d1a 100644 (file)
@@ -741,7 +741,7 @@ static struct clk_alpha_pll *video_cc_kaanapali_plls[] = {
        &video_cc_pll3,
 };
 
-static u32 video_cc_kaanapali_critical_cbcrs[] = {
+static const u32 video_cc_kaanapali_critical_cbcrs[] = {
        0x817c, /* VIDEO_CC_AHB_CLK */
        0x81bc, /* VIDEO_CC_SLEEP_CLK */
        0x81b0, /* VIDEO_CC_TS_XO_CLK */
index 012a13f8fb0b571ad673471e1d6f9d7fe857093b..3cce34e8c71a9a246bb6e1a396415b20e117aa11 100644 (file)
@@ -345,7 +345,7 @@ static struct clk_alpha_pll *video_cc_milos_plls[] = {
        &video_cc_pll0,
 };
 
-static u32 video_cc_milos_critical_cbcrs[] = {
+static const u32 video_cc_milos_critical_cbcrs[] = {
        0x80f4, /* VIDEO_CC_AHB_CLK */
        0x8140, /* VIDEO_CC_SLEEP_CLK */
        0x8124, /* VIDEO_CC_XO_CLK */
index 338ab803d56a439dc6fe279a60c22c3bacefa12e..3203cb938ad1ba713df53cfa3894f968a0f346b8 100644 (file)
@@ -283,7 +283,7 @@ static struct clk_alpha_pll *video_cc_qcs615_plls[] = {
        &video_pll0,
 };
 
-static u32 video_cc_qcs615_critical_cbcrs[] = {
+static const u32 video_cc_qcs615_critical_cbcrs[] = {
        0xab8, /* VIDEO_CC_XO_CLK */
 };
 
index acd0928be1f6922bf64c212db12c1a373f7365db..18b191f598b596fcb31d3da11a780bc33c495ab4 100644 (file)
@@ -413,7 +413,7 @@ static struct clk_alpha_pll *video_cc_sm8450_plls[] = {
        &video_cc_pll1,
 };
 
-static u32 video_cc_sm8450_critical_cbcrs[] = {
+static const u32 video_cc_sm8450_critical_cbcrs[] = {
        0x80e4, /* VIDEO_CC_AHB_CLK */
        0x8114, /* VIDEO_CC_XO_CLK */
        0x8130, /* VIDEO_CC_SLEEP_CLK */
index 32a6505abe265472de4059c4a048f731fdbf1dfe..4e35964f08038b3017ccf5a76b825d7cc2cd9b99 100644 (file)
@@ -536,13 +536,13 @@ static struct clk_alpha_pll *video_cc_sm8550_plls[] = {
        &video_cc_pll1,
 };
 
-static u32 video_cc_sm8550_critical_cbcrs[] = {
+static const u32 video_cc_sm8550_critical_cbcrs[] = {
        0x80f4, /* VIDEO_CC_AHB_CLK */
        0x8124, /* VIDEO_CC_XO_CLK */
        0x8140, /* VIDEO_CC_SLEEP_CLK */
 };
 
-static u32 video_cc_sm8650_critical_cbcrs[] = {
+static const u32 video_cc_sm8650_critical_cbcrs[] = {
        0x80f4, /* VIDEO_CC_AHB_CLK */
        0x8124, /* VIDEO_CC_XO_CLK */
        0x8150, /* VIDEO_CC_SLEEP_CLK */
index 7e77822c132c1b9cd80d246bc239f7236e698660..e9414390a3ccdd2ca43e1d4fafe5b6f385347454 100644 (file)
@@ -392,7 +392,7 @@ static struct clk_alpha_pll *video_cc_sm8750_plls[] = {
        &video_cc_pll0,
 };
 
-static u32 video_cc_sm8750_critical_cbcrs[] = {
+static const u32 video_cc_sm8750_critical_cbcrs[] = {
        0x80a4, /* VIDEO_CC_AHB_CLK */
        0x80f8, /* VIDEO_CC_SLEEP_CLK */
        0x80d4, /* VIDEO_CC_XO_CLK */