re PR target/84786 ([miscompilation] vunpcklpd accessing xmm16-22 targeting KNL)

	PR target/84786
	* config/i386/sse.md (vshift_count): New mode attr.
	(<shift_insn><mode>3<mask_name>): Use <vshift_count>N instead of vN
	as last operand's constraint for VI2_AVX2_AVX512BW shifts.  Use YvN
	instead of vN as last operand's constraint for VI48_AVX2 shifts.

	* gcc.target/i386/avx512f-pr84786-3.c: New test.

From-SVN: r262103

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 34b832208bcf85dc068ad3e5aa4a40d160ad1e67..c369c25f29d6cabc2a095e1ca21d140b2a1691de 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,11 @@
 2018-06-25  Jakub Jelinek  <jakub@redhat.com>
 
+       PR target/84786
+       * config/i386/sse.md (vshift_count): New mode attr.
+       (<shift_insn><mode>3<mask_name>): Use <vshift_count>N instead of vN
+       as last operand's constraint for VI2_AVX2_AVX512BW shifts.  Use YvN
+       instead of vN as last operand's constraint for VI48_AVX2 shifts.
+
        Backported from mainline
        2018-06-20  Jakub Jelinek  <jakub@redhat.com>
 

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e5ff0078c69186836d85b57e8f414edfbfdd2651..9f28b142a74932aaa4dd2972af6fa06afdbe9b31 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -10546,30 +10546,49 @@
        (const_string "0")))
    (set_attr "mode" "<sseinsnmode>")])
 
+(define_mode_attr vshift_count
+  [(V32HI "v") (V16HI "x") (V8HI "x")])
+
 (define_insn "<shift_insn><mode>3<mask_name>"
-  [(set (match_operand:VI2_AVX2_AVX512BW 0 "register_operand" "=x,v")
+  [(set (match_operand:VI2_AVX2_AVX512BW 0 "register_operand" "=x,v,v")
        (any_lshift:VI2_AVX2_AVX512BW
-         (match_operand:VI2_AVX2_AVX512BW 1 "register_operand" "0,v")
-         (match_operand:DI 2 "nonmemory_operand" "xN,vN")))]
+         (match_operand:VI2_AVX2_AVX512BW 1 "register_operand" "0,v,v")
+         (match_operand:DI 2 "nonmemory_operand" "xN,<vshift_count>N,vN")))]
   "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
   "@
    p<vshift><ssemodesuffix>\t{%2, %0|%0, %2}
+   vp<vshift><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}
    vp<vshift><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
-  [(set_attr "isa" "noavx,avx")
+  [(set_attr "isa" "noavx,avx,avx512vl")
    (set_attr "type" "sseishft")
    (set (attr "length_immediate")
      (if_then_else (match_operand 2 "const_int_operand")
        (const_string "1")
        (const_string "0")))
-   (set_attr "prefix_data16" "1,*")
-   (set_attr "prefix" "orig,vex")
+   (set_attr "prefix_data16" "1,*,*")
+   (set_attr "prefix" "orig,vex,vex")
+   (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "*<shift_insn><mode>3<mask_name>_1"
+  [(set (match_operand:VI48_AVX2 0 "register_operand" "=v")
+       (any_lshift:VI48_AVX2
+         (match_operand:VI48_AVX2 1 "register_operand" "v")
+         (match_operand:DI 2 "nonmemory_operand" "vN")))]
+  "TARGET_AVX512BW && TARGET_AVX512VL"
+  "vp<vshift><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+  [(set_attr "type" "sseishft")
+   (set (attr "length_immediate")
+     (if_then_else (match_operand 2 "const_int_operand")
+       (const_string "1")
+       (const_string "0")))
+   (set_attr "prefix" "evex")
    (set_attr "mode" "<sseinsnmode>")])
 
 (define_insn "<shift_insn><mode>3<mask_name>"
   [(set (match_operand:VI48_AVX2 0 "register_operand" "=x,x,v")
        (any_lshift:VI48_AVX2
          (match_operand:VI48_AVX2 1 "register_operand" "0,x,v")
-         (match_operand:DI 2 "nonmemory_operand" "xN,xN,vN")))]
+         (match_operand:DI 2 "nonmemory_operand" "xN,xN,xN")))]
   "TARGET_SSE2 && <mask_mode512bit_condition>"
   "@
    p<vshift><ssemodesuffix>\t{%2, %0|%0, %2}

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ccbbdae8d80a9a09697ca37e30892fd94e1a9d2a..03fab0c0151b067d24727cb2e792aef7fccedc8a 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,8 @@
 2018-06-25  Jakub Jelinek  <jakub@redhat.com>
 
+       PR target/84786
+       * gcc.target/i386/avx512f-pr84786-3.c: New test.
+
        Backported from mainline
        2018-06-20  Jakub Jelinek  <jakub@redhat.com>
 

diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr84786-3.c b/gcc/testsuite/gcc.target/i386/avx512f-pr84786-3.c
new file mode 100644 (file)
index 0000000..4d125b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-pr84786-3.c
@@ -0,0 +1,50 @@
+/* PR target/84786 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mavx512f -mno-avx512vl -O2" } */
+
+#include <x86intrin.h>
+
+__m512i v;
+__m128i w;
+
+__m128i
+foo (__m128i x, int y)
+{
+  __m128i z;
+#define A(n) register __m512i zmm##n __asm ("zmm" #n);
+#define B A(1) A(2) A(3) A(4) A(5) A(6) A(7) \
+         A(8) A(9) A(10) A(11) A(12) A(13) A(14)
+  B
+#undef A
+#define A(n) asm volatile ("" : "=v" (zmm##n) : "0" (v));
+  B
+  asm volatile ("" : "=x" (z) : "0" (w));
+  x = _mm_srli_epi16 (x, y);
+  asm volatile ("" : : "x" (z));
+#undef A
+#define A(n) asm volatile ("" : : "v" (zmm##n));
+  B
+  return x;
+}
+
+__m256i
+bar (__m256i x, int y)
+{
+  __m128i z;
+#undef A
+#define A(n) register __m512i zmm##n __asm ("zmm" #n);
+  B
+#undef A
+#define A(n) asm volatile ("" : "=v" (zmm##n) : "0" (v));
+  B
+  asm volatile ("" : "=x" (z) : "0" (w));
+  x = _mm256_slli_epi16 (x, y);
+  asm volatile ("" : : "x" (z));
+#undef A
+#define A(n) asm volatile ("" : : "v" (zmm##n));
+  B
+  return x;
+}
+
+/* { dg-final { scan-assembler-not "vpsrlw\[\^\n\r]*xmm(1\[6-9]|\[23]\[0-9])" } } */
+/* { dg-final { scan-assembler-not "vpsllw\[\^\n\r]*xmm(1\[6-9]|\[23]\[0-9])" } } */