]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
net: wangxun: revert the adjustment of the IRQ vector sequence
authorJiawen Wu <jiawenwu@trustnetic.com>
Tue, 1 Jul 2025 06:30:29 +0000 (14:30 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 17 Jul 2025 16:44:04 +0000 (18:44 +0200)
commit e37546ad1f9b2c777d3a21d7e50ce265ee3dece8 upstream.

Due to hardware limitations of NGBE, queue IRQs can only be requested
on vector 0 to 7. When the number of queues is set to the maximum 8,
the PCI IRQ vectors are allocated from 0 to 8. The vector 0 is used by
MISC interrupt, and althrough the vector 8 is used by queue interrupt,
it is unable to receive packets. This will cause some packets to be
dropped when RSS is enabled and they are assigned to queue 8.

So revert the adjustment of the MISC IRQ location, to make it be the
last one in IRQ vectors.

Fixes: 937d46ecc5f9 ("net: wangxun: add ethtool_ops for channel number")
Cc: stable@vger.kernel.org
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
Reviewed-by: Larysa Zaremba <larysa.zaremba@intel.com>
Link: https://patch.msgid.link/20250701063030.59340-3-jiawenwu@trustnetic.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/net/ethernet/wangxun/libwx/wx_lib.c
drivers/net/ethernet/wangxun/libwx/wx_type.h
drivers/net/ethernet/wangxun/ngbe/ngbe_main.c
drivers/net/ethernet/wangxun/ngbe/ngbe_type.h
drivers/net/ethernet/wangxun/txgbe/txgbe_irq.c
drivers/net/ethernet/wangxun/txgbe/txgbe_type.h

index f77bdf732f5f375897055124427a6c1a668852a1..4eac40c4e8514e85c192874c1fa37b3ad915f065 100644 (file)
@@ -1680,7 +1680,7 @@ static void wx_set_num_queues(struct wx *wx)
  */
 static int wx_acquire_msix_vectors(struct wx *wx)
 {
-       struct irq_affinity affd = { .pre_vectors = 1 };
+       struct irq_affinity affd = { .post_vectors = 1 };
        int nvecs, i;
 
        /* We start by asking for one vector per queue pair */
@@ -1717,16 +1717,17 @@ static int wx_acquire_msix_vectors(struct wx *wx)
                return nvecs;
        }
 
-       wx->msix_entry->entry = 0;
-       wx->msix_entry->vector = pci_irq_vector(wx->pdev, 0);
        nvecs -= 1;
        for (i = 0; i < nvecs; i++) {
                wx->msix_q_entries[i].entry = i;
-               wx->msix_q_entries[i].vector = pci_irq_vector(wx->pdev, i + 1);
+               wx->msix_q_entries[i].vector = pci_irq_vector(wx->pdev, i);
        }
 
        wx->num_q_vectors = nvecs;
 
+       wx->msix_entry->entry = nvecs;
+       wx->msix_entry->vector = pci_irq_vector(wx->pdev, nvecs);
+
        return 0;
 }
 
@@ -2182,7 +2183,6 @@ static void wx_set_ivar(struct wx *wx, s8 direction,
                wr32(wx, WX_PX_MISC_IVAR, ivar);
        } else {
                /* tx or rx causes */
-               msix_vector += 1; /* offset for queue vectors */
                msix_vector |= WX_PX_IVAR_ALLOC_VAL;
                index = ((16 * (queue & 1)) + (8 * direction));
                ivar = rd32(wx, WX_PX_IVAR(queue >> 1));
@@ -2220,7 +2220,7 @@ void wx_write_eitr(struct wx_q_vector *q_vector)
 
        itr_reg |= WX_PX_ITR_CNT_WDIS;
 
-       wr32(wx, WX_PX_ITR(v_idx + 1), itr_reg);
+       wr32(wx, WX_PX_ITR(v_idx), itr_reg);
 }
 
 /**
@@ -2266,9 +2266,9 @@ void wx_configure_vectors(struct wx *wx)
                wx_write_eitr(q_vector);
        }
 
-       wx_set_ivar(wx, -1, 0, 0);
+       wx_set_ivar(wx, -1, 0, v_idx);
        if (pdev->msix_enabled)
-               wr32(wx, WX_PX_ITR(0), 1950);
+               wr32(wx, WX_PX_ITR(v_idx), 1950);
 }
 EXPORT_SYMBOL(wx_configure_vectors);
 
index 4c545b2aa997cb56a172e1a0c0e3a8b76db69369..3a9c226567f8013c0965dcfd80a2b5bffaa83b26 100644 (file)
@@ -1242,7 +1242,7 @@ struct wx {
 };
 
 #define WX_INTR_ALL (~0ULL)
-#define WX_INTR_Q(i) BIT((i) + 1)
+#define WX_INTR_Q(i) BIT((i))
 
 /* register operations */
 #define wr32(a, reg, value)    writel((value), ((a)->hw_addr + (reg)))
index 91b3055a5a9f599dc1efb9ced87a6ad8dafb08b9..d37fd9004b410c7baabf628e3fba2497b558965c 100644 (file)
@@ -155,7 +155,7 @@ static void ngbe_irq_enable(struct wx *wx, bool queues)
        if (queues)
                wx_intr_enable(wx, NGBE_INTR_ALL);
        else
-               wx_intr_enable(wx, NGBE_INTR_MISC);
+               wx_intr_enable(wx, NGBE_INTR_MISC(wx));
 }
 
 /**
index 992adbb98c7d127b71137b2b69fe412ffdc8d0f6..9e277a9330c94bc731e39b0ff5211f93edd35978 100644 (file)
@@ -85,7 +85,7 @@
 #define NGBE_PX_MISC_IC_TIMESYNC               BIT(11) /* time sync */
 
 #define NGBE_INTR_ALL                          0x1FF
-#define NGBE_INTR_MISC                         BIT(0)
+#define NGBE_INTR_MISC(A)                      BIT((A)->num_q_vectors)
 
 #define NGBE_PHY_CONFIG(reg_offset)            (0x14000 + ((reg_offset) * 4))
 #define NGBE_CFG_LAN_SPEED                     0x14440
index 44547e69c026feb3a109fdb11c62eec9eabbc8d6..07a6e7b54607115b318807677c9f3c48439367f1 100644 (file)
@@ -21,7 +21,7 @@ void txgbe_irq_enable(struct wx *wx, bool queues)
        wr32(wx, WX_PX_MISC_IEN, TXGBE_PX_MISC_IEN_MASK);
 
        /* unmask interrupt */
-       wx_intr_enable(wx, TXGBE_INTR_MISC);
+       wx_intr_enable(wx, TXGBE_INTR_MISC(wx));
        if (queues)
                wx_intr_enable(wx, TXGBE_INTR_QALL(wx));
 }
@@ -147,7 +147,7 @@ static irqreturn_t txgbe_misc_irq_thread_fn(int irq, void *data)
                nhandled++;
        }
 
-       wx_intr_enable(wx, TXGBE_INTR_MISC);
+       wx_intr_enable(wx, TXGBE_INTR_MISC(wx));
        return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
 }
 
index f423012dec2256489063158ab688b196b6a78151..b91f2f7bd1fb5d323411320e23d11aa82766f247 100644 (file)
@@ -280,8 +280,8 @@ struct txgbe_fdir_filter {
 #define TXGBE_DEFAULT_RX_WORK           128
 #endif
 
-#define TXGBE_INTR_MISC       BIT(0)
-#define TXGBE_INTR_QALL(A)    GENMASK((A)->num_q_vectors, 1)
+#define TXGBE_INTR_MISC(A)    BIT((A)->num_q_vectors)
+#define TXGBE_INTR_QALL(A)    (TXGBE_INTR_MISC(A) - 1)
 
 #define TXGBE_MAX_EITR        GENMASK(11, 3)