arm64: dts: qcom: sm8650: extend the register range for UFS ICE

The full register range for ICE on sm8650 is 0x18000 so update the
crypto node.

Reviewed-by: Om Prakash Singh <quic_omprsing@quicinc.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Co-developed-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20241007-wrapped-keys-dts-v8-1-05ee041f2fc1@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 173e092b15e2fa7e9d1c9157bf86cda429db5e09..3d8a807a81c9c15eeeaadf624a8e7f085b68ae9e 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2595,7 +2595,7 @@
                ice: crypto@1d88000 {
                        compatible = "qcom,sm8650-inline-crypto-engine",
                                     "qcom,inline-crypto-engine";
-                       reg = <0 0x01d88000 0 0x8000>;
+                       reg = <0 0x01d88000 0 0x18000>;
 
                        clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
                };