RISC-V: Handle vlenb correctly in unwinding

gcc/ChangeLog:

	* config/riscv/riscv.h (RISCV_DWARF_VLENB): New.
	(DWARF_FRAME_REGISTERS): New.
	(DWARF_REG_TO_UNWIND_COLUMN): New.

libgcc/ChangeLog:

	* config.host (riscv*-*-*): Add config/riscv/value-unwind.h.
	* config/riscv/value-unwind.h: New.

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 120faf17c06601cfb1588e581900942fe2ee9c16..5bc7f2f467d9f6e8c4efc4faa9f96f27a7854a40 100644 (file)
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1088,4 +1088,11 @@ extern void riscv_remove_unneeded_save_restore_calls (void);
 
 #define REGMODE_NATURAL_SIZE(MODE) riscv_regmode_natural_size (MODE)
 
+#define RISCV_DWARF_VLENB (4096 + 0xc22)
+
+#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 1 /* VLENB */)
+
+#define DWARF_REG_TO_UNWIND_COLUMN(REGNO) \
+  ((REGNO == RISCV_DWARF_VLENB) ? (FIRST_PSEUDO_REGISTER + 1) : REGNO)
+
 #endif /* ! GCC_RISCV_H */

diff --git a/libgcc/config.host b/libgcc/config.host
index 70d47e08e40458a7a96d73ed492f43dcf82702f1..b9975de902357576003cf391850fef2dc336aee1 100644 (file)
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1559,6 +1559,9 @@ aarch64*-*-*)
        # ILP32 needs an extra header for unwinding
        tm_file="${tm_file} aarch64/value-unwind.h"
        ;;
+riscv*-*-*)
+       tm_file="${tm_file} riscv/value-unwind.h"
+       ;;
 esac
 
 # Setup to build a shared libgcc for VxWorks when that was requested,

diff --git a/libgcc/config/riscv/value-unwind.h b/libgcc/config/riscv/value-unwind.h
new file mode 100644 (file)
index 0000000..d7efdc1
--- /dev/null
+++ b/libgcc/config/riscv/value-unwind.h
@@ -0,0 +1,39 @@
+/* Store register values as _Unwind_Word type in DWARF2 EH unwind context.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+/* Return the value of the VLENB register.  This should only be
+   called if we know this is an vector extension enabled RISC-V host.  */
+static inline long
+riscv_vlenb (void)
+{
+  register long vlenb asm ("a0");
+  /* 0xc2202573 == csrr a0, 0xc22 */
+  asm (".insn 0xc2202573" : "=r"(vlenb));
+  return vlenb;
+}
+
+/* Lazily provide a value for VLENB, so that we don't try to execute RVV
+   instructions unless we know they're needed.  */
+#define DWARF_LAZY_REGISTER_VALUE(REGNO, VALUE) \
+  ((REGNO) == RISCV_DWARF_VLENB && ((*VALUE) = riscv_vlenb (), 1))