drm/msm/dpu: Fix adjusted mode clock check for 3d merge

commit f5d079564c44baaeedf5e25f4b943aa042ea0eb1 upstream.

Since 3D merge allows for larger modes to be supported across 2 layer
mixers, filter modes based on adjusted mode clock / 2 when 3d merge is
supported.

Reported-by: Abel Vesa <abel.vesa@linaro.org>
Fixes: 62b7d6835288 ("drm/msm/dpu: Filter modes based on adjusted mode clock")
Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Tested-by: Abel Vesa <abel.vesa@linaro.org>
Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/676353/
Link: https://lore.kernel.org/r/20250923-modeclk-fix-v2-1-01fcd0b2465a@oss.qualcomm.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index d59512e45af0531ab6bb59a2c8fdf42129ebef40..7a6b344ca3fb83a49739d144892d283732eb3af7 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1546,6 +1546,9 @@ static enum drm_mode_status dpu_crtc_mode_valid(struct drm_crtc *crtc,
        adjusted_mode_clk = dpu_core_perf_adjusted_mode_clk(mode->clock,
                                                            dpu_kms->perf.perf_cfg);
 
+       if (dpu_kms->catalog->caps->has_3d_merge)
+               adjusted_mode_clk /= 2;
+
        /*
         * The given mode, adjusted for the perf clock factor, should not exceed
         * the max core clock rate