SH: Avoid FPUL for fp-constant loads

For an fp-constant loaded from the constant pool, there is only one
movsf_ie alternative with the multi-class constraint "fy".
Change the FPUL alternative to '*y' so that IRA costs it as FP_REGS.
LRA still accepts the FPUL variant when it is really needed but treats
it as more expensive, which discourages FPUL usage for regular fp-regs.

gcc/ChangeLog:

	PR target/116709
	* config/sh/sh.md (movsf_ie): Mark constant-pool load FPUL
	alternative with '*'.

diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 4a15af7d3586fe84e20ece7183d7847c1c9ac60e..d5f6c80030a6b67ecb6cb87557bbd1048420224c 100644 (file)
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -6196,11 +6196,11 @@
 ;; when the destination changes mode.
 (define_insn "movsf_ie"
   [(set (match_operand:SF 0 "general_movdst_operand"
-                               "=f,r,f,f,fy, f,m, r, r,m,f,y,y,rf,r,y,<,y,y")
+                               "=f,r,f,f,f*y,f,m, r, r,m,f,y,y,rf,r,y,<,y,y")
        (match_operand:SF 1 "general_movsrc_operand"
-                               " f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
+                               " f,r,G,H, FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
    (use (reg:SI FPSCR_MODES_REG))
-   (clobber (match_scratch:SI 2 "=X,X,X,X,&z, X,X, X, X,X,X,X,X, y,X,X,X,X,X"))]
+   (clobber (match_scratch:SI 2 "=X,X,X,X, &z,X,X, X, X,X,X,X,X, y,X,X,X,X,X"))]
   "TARGET_SH2E
    && (arith_reg_operand (operands[0], SFmode)
        || fpul_operand (operands[0], SFmode)

diff --git a/gcc/testsuite/gcc.target/sh/pr116709.c b/gcc/testsuite/gcc.target/sh/pr116709.c
new file mode 100644 (file)
index 0000000..e07c196
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/pr116709.c
@@ -0,0 +1,10 @@
+/* Verify that SFmode loads into FP registers are not ferried through FPUL.  */
+/* { dg-do compile { target { any_fpu } } }  */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "fpul" } } */
+
+_Complex float
+test_00 (void)
+{
+  return __builtin_complex (12.3f, 15.4f);
+}