arm64: dts: ti: k3-am69-sk: Add bootph-all property to enable Ethernet boot

Ethernet boot requires CPSW nodes to be present starting from R5 SPL
stage. Add bootph-all property to required nodes to enable Ethernet boot
for SK-AM69.

Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
Link: https://lore.kernel.org/r/20250709105326.232608-5-c-vankar@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
index f28375629739cbb76567a805d9655a1cd19d4d83..a09dcb812648f02a524eb938474dc1a0bfe8017a 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
@@ -568,6 +568,7 @@
                        J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
                        J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
                >;
+               bootph-all;
        };
 
        mcu_mdio_pins_default: mcu-mdio-default-pins {
@@ -575,6 +576,7 @@
                        J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
                        J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
                >;
+               bootph-all;
        };
 
        mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins {
@@ -630,6 +632,14 @@
        };
 };
 
+&cpsw_mac_syscon {
+       bootph-all;
+};
+
+&phy_gmii_sel {
+       bootph-all;
+};
+
 &mailbox0_cluster0 {
        status = "okay";
        interrupts = <436>;
@@ -968,6 +978,7 @@
 &davinci_mdio {
        mcu_phy0: ethernet-phy@0 {
                reg = <0>;
+               bootph-all;
                ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
                ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
                ti,min-output-impedance;
@@ -978,6 +989,7 @@
        status = "okay";
        phy-mode = "rgmii-rxid";
        phy-handle = <&mcu_phy0>;
+       bootph-all;
 };
 
 &mcu_r5fss0_core0 {