It could cause weired spill in RA when register pressure is high.
gcc/ChangeLog:
PR target/117562
* config/i386/sse.md (vec_unpacks_hi_v4sf): Initialize
operands[2] with CONST0_RTX.
(cherry picked from commit
ba4cf2e296d8d5950c3d356fa6b6efcad00d0189)
(match_dup 2)
(parallel [(const_int 0) (const_int 1)]))))]
"TARGET_SSE2"
- "operands[2] = gen_reg_rtx (V4SFmode);")
+{
+ operands[2] = gen_reg_rtx (V4SFmode);
+ emit_move_insn (operands[2], CONST0_RTX (V4SFmode));
+})
(define_expand "vec_unpacks_hi_v8sf"
[(set (match_dup 2)