arm64: dts: qcom: qcs615: Add CPU and LLCC BWMON support

Add CPU and LLCC BWMON nodes and their corresponding opp tables to
support bandwidth monitoring on QCS615 SoC. This is necessary to enable
power management and optimize system performance from the perspective of
dynamically changing LLCC and DDR frequencies.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241218-add_bwmon_support_for_qcs615-v1-2-680d798a19e5@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index c0e4b376a1c61153ee05f717515eccad7cab93f4..45a4d9a76163d288be7a33c58d638746258d6c4c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -2753,6 +2753,78 @@
                        clock-names = "apb_pclk";
                };
 
+               pmu@90b6300 {
+                       compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon";
+                       reg = <0x0 0x090b6300 0x0 0x600>;
+                       interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+                       interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+                       operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+                       cpu_bwmon_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-0 {
+                                       opp-peak-kBps = <12896000>;
+                               };
+
+                               opp-1 {
+                                       opp-peak-kBps = <14928000>;
+                               };
+                       };
+               };
+
+               pmu@90cd000 {
+                       compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+                       reg = <0x0 0x090cd000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>;
+                       interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+                       operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+                       llcc_bwmon_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-0 {
+                                       opp-peak-kBps = <800000>;
+                               };
+
+                               opp-1 {
+                                       opp-peak-kBps = <1200000>;
+                               };
+
+                               opp-2 {
+                                       opp-peak-kBps = <1804800>;
+                               };
+
+                               opp-3 {
+                                       opp-peak-kBps = <2188800>;
+                               };
+
+                               opp-4 {
+                                       opp-peak-kBps = <2726400>;
+                               };
+
+                               opp-5 {
+                                       opp-peak-kBps = <3072000>;
+                               };
+
+                               opp-6 {
+                                       opp-peak-kBps = <4070400>;
+                               };
+
+                               opp-7 {
+                                       opp-peak-kBps = <5414400>;
+                               };
+
+                               opp-8 {
+                                       opp-peak-kBps = <6220800>;
+                               };
+                       };
+               };
+
                dc_noc: interconnect@9160000 {
                        reg = <0x0 0x09160000 0x0 0x3200>;
                        compatible = "qcom,qcs615-dc-noc";