drm/amd/display: Fix for test crash due to power gating

[ Upstream commit 0bf6b216d4783cb51f9af05a49d3cce4fc22dc24 ]

[Why/How]
Call power gating routine only if it is defined.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Sridevi Arvindekar <sarvinde@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 9d3946065620a17df5f5c6cf04dc7c382ca9eb7f..f7b72b24b7509b9869e7f666f57a8b544ec6b859 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -3129,7 +3129,8 @@ void dcn20_fpga_init_hw(struct dc *dc)
                res_pool->dccg->funcs->dccg_init(res_pool->dccg);
 
        //Enable ability to power gate / don't force power on permanently
-       hws->funcs.enable_power_gating_plane(hws, true);
+       if (hws->funcs.enable_power_gating_plane)
+               hws->funcs.enable_power_gating_plane(hws, true);
 
        // Specific to FPGA dccg and registers
        REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);