mips64: make cavium CvmCount register accessible via rdhwr

Fixes reported issue BZ #346031.

Patch by Crestez Dan Leonard.

git-svn-id: svn://svn.valgrind.org/vex/trunk@3166

diff --git a/VEX/priv/guest_mips_helpers.c b/VEX/priv/guest_mips_helpers.c
index 863efda8337317ff9893277535b539f0093c2147..ae9382d28a7587dbe3319323bee1e270303b4ee8 100644 (file)
--- a/VEX/priv/guest_mips_helpers.c
+++ b/VEX/priv/guest_mips_helpers.c
@@ -1085,6 +1085,10 @@ UInt mips32_dirtyhelper_rdhwr ( UInt rt, UInt rd )
          __asm__ __volatile__("rdhwr %0, $1\n\t" : "=r" (x) );
          break;
 
+      case 31:  /* x = CVMX_get_cycles() */
+         __asm__ __volatile__("rdhwr %0, $31\n\t" : "=r" (x) );
+         break;
+
       default:
          vassert(0);
          break;
@@ -1100,6 +1104,10 @@ ULong mips64_dirtyhelper_rdhwr ( ULong rt, ULong rd )
          __asm__ __volatile__("rdhwr %0, $1\n\t" : "=r" (x) );
          break;
 
+      case 31:  /* x = CVMX_get_cycles() */
+         __asm__ __volatile__("rdhwr %0, $31\n\t" : "=r" (x) );
+         break;
+
       default:
          vassert(0);
          break;

diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c
index 887a1fc2397c7fa5e0d5212f8dd83cc1b04b33f3..c27540bc5ff0e82c98cb19f3a0b25dc57edebc57 100644 (file)
--- a/VEX/priv/guest_mips_toIR.c
+++ b/VEX/priv/guest_mips_toIR.c
@@ -15121,7 +15121,10 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *,
             if (rd == 29) {
                putIReg(rt, getULR());
 #if defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 2))
-            } else if (rd == 1) {
+            } else if (rd == 1
+                       || (rd == 31
+                           && VEX_MIPS_COMP_ID(archinfo->hwcaps)
+                                                    == VEX_PRID_COMP_CAVIUM)) {
                if (mode64) {
                   IRTemp   val  = newTemp(Ity_I64);
                   IRExpr** args = mkIRExprVec_2 (mkU64(rt), mkU64(rd));