net/mlx5: Introduce data placement ordering bits

Introduce out-of-order (OOO) data placement (DP) IFC related bits to
support OOO DP QP.

Signed-off-by: Edward Srouji <edwards@nvidia.com>
Reviewed-by: Yishai Hadas <yishaih@nvidia.com>
Link: https://patch.msgid.link/f30e5cbb5459fd02f27f35909bb545cab346b58b.1725362773.git.leon@kernel.org
Signed-off-by: Leon Romanovsky <leon@kernel.org>

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 96d369112bfa037d7d05ed6ca1310115c6dbd60f..2a037843b11727fb1da843baed7aedc0a33dc2c4 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1872,7 +1872,11 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         reserved_at_328[0x2];
        u8         relaxed_ordering_read[0x1];
        u8         log_max_pd[0x5];
-       u8         reserved_at_330[0x5];
+       u8         dp_ordering_ooo_all_ud[0x1];
+       u8         dp_ordering_ooo_all_uc[0x1];
+       u8         dp_ordering_ooo_all_xrc[0x1];
+       u8         dp_ordering_ooo_all_dc[0x1];
+       u8         dp_ordering_ooo_all_rc[0x1];
        u8         pcie_reset_using_hotreset_method[0x1];
        u8         pci_sync_for_fw_update_with_driver_unload[0x1];
        u8         vnic_env_cnt_steering_fail[0x1];
@@ -2094,7 +2098,9 @@ struct mlx5_ifc_cmd_hca_cap_2_bits {
        u8         reserved_at_0[0x80];
 
        u8         migratable[0x1];
-       u8         reserved_at_81[0x11];
+       u8         reserved_at_81[0x7];
+       u8         dp_ordering_force[0x1];
+       u8         reserved_at_89[0x9];
        u8         query_vuid[0x1];
        u8         reserved_at_93[0x5];
        u8         umr_log_entity_size_5[0x1];
@@ -3524,7 +3530,8 @@ struct mlx5_ifc_qpc_bits {
        u8         latency_sensitive[0x1];
        u8         reserved_at_24[0x1];
        u8         drain_sigerr[0x1];
-       u8         reserved_at_26[0x2];
+       u8         reserved_at_26[0x1];
+       u8         dp_ordering_force[0x1];
        u8         pd[0x18];
 
        u8         mtu[0x3];
@@ -3597,7 +3604,8 @@ struct mlx5_ifc_qpc_bits {
        u8         rae[0x1];
        u8         reserved_at_493[0x1];
        u8         page_offset[0x6];
-       u8         reserved_at_49a[0x3];
+       u8         reserved_at_49a[0x2];
+       u8         dp_ordering_1[0x1];
        u8         cd_slave_receive[0x1];
        u8         cd_slave_send[0x1];
        u8         cd_master[0x1];
@@ -4507,7 +4515,8 @@ struct mlx5_ifc_dctc_bits {
        u8         state[0x4];
        u8         reserved_at_8[0x18];
 
-       u8         reserved_at_20[0x8];
+       u8         reserved_at_20[0x7];
+       u8         dp_ordering_force[0x1];
        u8         user_index[0x18];
 
        u8         reserved_at_40[0x8];
@@ -4522,7 +4531,9 @@ struct mlx5_ifc_dctc_bits {
        u8         latency_sensitive[0x1];
        u8         rlky[0x1];
        u8         free_ar[0x1];
-       u8         reserved_at_73[0xd];
+       u8         reserved_at_73[0x1];
+       u8         dp_ordering_1[0x1];
+       u8         reserved_at_75[0xb];
 
        u8         reserved_at_80[0x8];
        u8         cs_res[0x8];