riscv: dts: microchip: use an mpfs specific l2 compatible

[ Upstream commit 0dec364ffeb6149aae572ded1e34d4b444c23be6 ]

PolarFire SoC does not have the same l2 cache controller as the fu540,
featuring an extra interrupt. Appease the devicetree checker overlords
by adding a PolarFire SoC specific compatible to fix the below sort of
warnings:

mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long

Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts")
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 9f5bce1488d932be3d4d4d41dfdfbcd67f3965fd..9bf37ef379509ca26102db4239af225a292ed146 100644 (file)
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -161,7 +161,7 @@
                ranges;
 
                cctrllr: cache-controller@2010000 {
-                       compatible = "sifive,fu540-c000-ccache", "cache";
+                       compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
                        reg = <0x0 0x2010000 0x0 0x1000>;
                        cache-block-size = <64>;
                        cache-level = <2>;