clk: mediaTek: mt8188: add clock tree type flags

Add clock tree type flags to the mt8188 clock tree structures. These
will be used later for parent lookup.

Link: https://patch.msgid.link/20260710-mtk-clk-parent-lookup-improvements-v2-11-f3f3a4a28dca@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>

diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c
index b82a6ab5452ceb42f16c8a791ea53a9b90f4a578..9cc7180f1e23d564c05c4af6b5067372f9ba804d 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8188.c
+++ b/drivers/clk/mediatek/clk-mt8188.c
@@ -89,6 +89,7 @@ static const struct mtk_clk_tree mt8188_apmixedsys_clk_tree = {
        .num_ext_clks = ARRAY_SIZE(ext_clock_rates),
        .plls = apmixed_plls,
        .num_plls = ARRAY_SIZE(apmixed_plls),
+       .type = MTK_CLK_TREE_APMIXED,
 };
 
 #define FIXED_CLK0(_id, _rate)                 \
@@ -1422,6 +1423,7 @@ static const struct mtk_clk_tree mt8188_topckgen_clk_tree = {
        .num_fdivs = ARRAY_SIZE(top_fixed_divs),
        .num_muxes = ARRAY_SIZE(top_muxes),
        .num_gates = ARRAY_SIZE(topckgen_cg_clks),
+       .type = MTK_CLK_TREE_TOPCKGEN,
 };
 
 static const struct mtk_gate_regs infra_ao0_cg_regs = {
@@ -1794,6 +1796,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
        .name = "mt8188-apmixedsys",
        .id = UCLASS_CLK,
        .of_match = mt8188_apmixed_compat,
+       .bind = mtk_common_clk_parent_bind,
        .probe = mt8188_apmixedsys_probe,
        .priv_auto = sizeof(struct mtk_clk_priv),
        .ops = &mtk_clk_apmixedsys_ops,
@@ -1804,6 +1807,7 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = {
        .name = "mt8188-topckgen",
        .id = UCLASS_CLK,
        .of_match = mt8188_topckgen_compat,
+       .bind = mtk_common_clk_parent_bind,
        .probe = mt8188_topckgen_probe,
        .priv_auto = sizeof(struct mtk_clk_priv),
        .ops = &mtk_clk_topckgen_ops,