dt-bindings: clock: Add Qualcomm QCS615 Display clock controller

Add DT bindings for the Display clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-4-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/qcom,qcs615-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcs615-dispcc.yaml
new file mode 100644 (file)
index 0000000..d566f19
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,qcs615-dispcc.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller on QCS615
+
+maintainers:
+  - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+  Qualcomm display clock control module provides the clocks, resets and power
+  domains on QCS615.
+
+  See also: include/dt-bindings/clock/qcom,qcs615-dispcc.h
+
+properties:
+  compatible:
+    const: qcom,qcs615-dispcc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: GPLL0 clock source from GCC
+      - description: Byte clock from DSI PHY0
+      - description: Pixel clock from DSI PHY0
+      - description: Pixel clock from DSI PHY1
+      - description: Display port PLL link clock
+      - description: Display port PLL VCO DIV clock
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/clock/qcom,qcs615-gcc.h>
+    clock-controller@af00000 {
+      compatible = "qcom,qcs615-dispcc";
+      reg = <0x0af00000 0x20000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
+               <&mdss_dsi0_phy 0>,
+               <&mdss_dsi0_phy 1>,
+               <&mdss_dsi1_phy 0>,
+               <&mdss_dp_phy 0>,
+               <&mdss_dp_vco 0>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...

diff --git a/include/dt-bindings/clock/qcom,qcs615-dispcc.h b/include/dt-bindings/clock/qcom,qcs615-dispcc.h
new file mode 100644 (file)
index 0000000..9a29945
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,qcs615-dispcc.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_QCS615_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_QCS615_H
+
+/* DISP_CC clocks */
+#define DISP_CC_MDSS_AHB_CLK                                   0
+#define DISP_CC_MDSS_AHB_CLK_SRC                               1
+#define DISP_CC_MDSS_BYTE0_CLK                                 2
+#define DISP_CC_MDSS_BYTE0_CLK_SRC                             3
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC                         4
+#define DISP_CC_MDSS_BYTE0_INTF_CLK                            5
+#define DISP_CC_MDSS_DP_AUX_CLK                                        6
+#define DISP_CC_MDSS_DP_AUX_CLK_SRC                            7
+#define DISP_CC_MDSS_DP_CRYPTO_CLK                             8
+#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC                         9
+#define DISP_CC_MDSS_DP_LINK_CLK                               10
+#define DISP_CC_MDSS_DP_LINK_CLK_SRC                           11
+#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC                       12
+#define DISP_CC_MDSS_DP_LINK_INTF_CLK                          13
+#define DISP_CC_MDSS_DP_PIXEL1_CLK                             14
+#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC                         15
+#define DISP_CC_MDSS_DP_PIXEL_CLK                              16
+#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC                          17
+#define DISP_CC_MDSS_ESC0_CLK                                  18
+#define DISP_CC_MDSS_ESC0_CLK_SRC                              19
+#define DISP_CC_MDSS_MDP_CLK                                   20
+#define DISP_CC_MDSS_MDP_CLK_SRC                               21
+#define DISP_CC_MDSS_MDP_LUT_CLK                               22
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK                          23
+#define DISP_CC_MDSS_PCLK0_CLK                                 24
+#define DISP_CC_MDSS_PCLK0_CLK_SRC                             25
+#define DISP_CC_MDSS_ROT_CLK                                   26
+#define DISP_CC_MDSS_ROT_CLK_SRC                               27
+#define DISP_CC_MDSS_RSCC_AHB_CLK                              28
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK                            29
+#define DISP_CC_MDSS_VSYNC_CLK                                 30
+#define DISP_CC_MDSS_VSYNC_CLK_SRC                             31
+#define DISP_CC_PLL0                                           32
+#define DISP_CC_XO_CLK                                         33
+
+/* DISP_CC power domains */
+#define MDSS_CORE_GDSC                                         0
+
+/* DISP_CC resets */
+#define DISP_CC_MDSS_CORE_BCR                                  0
+#define DISP_CC_MDSS_RSCC_BCR                                  1
+
+#endif