drm/i915/xelpg: Extend driver code of Xe_LPG to Xe_LPG+

[ Upstream commit 84bf82f4f8661930a134a1d86bde16f7d8bcd699 ]

Xe_LPG+ (IP version 12.74) should take the same general code
paths as Xe_LPG (versions 12.70 and 12.71).

Xe_LPG+'s workaround list will be handled by the next patch.

Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240108122738.14399-3-haridhar.kalvala@intel.com
Stable-dep-of: 9d3d9776bd3b ("drm/i915: Disable RPG during live selftest")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index d9bb352b8baab781e174dfb4e90e8a7414abfc37..0729ab5955171e005334be3d05dd2df6179b7afc 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1218,7 +1218,8 @@ static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine)
                        num = ARRAY_SIZE(xelpmp_regs);
                }
        } else {
-               if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) ||
+               if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 74) ||
+                   GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) ||
                    GRAPHICS_VER_FULL(i915) == IP_VER(12, 70) ||
                    GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) ||
                    GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) {

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 353f93baaca051d1c21a7fd361c43a2efa488c72..25c1023eb5f9fa5afd63fc48c3847e2a57cdaafd 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -495,7 +495,7 @@ static unsigned int get_mocs_settings(struct drm_i915_private *i915,
        memset(table, 0, sizeof(struct drm_i915_mocs_table));
 
        table->unused_entries_index = I915_MOCS_PTE;
-       if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) {
+       if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 74))) {
                table->size = ARRAY_SIZE(mtl_mocs_table);
                table->table = mtl_mocs_table;
                table->n_entries = MTL_NUM_MOCS_ENTRIES;

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 6e8c182b2559e7b52c3ba61dd7d8944fc264d4b0..483d557858816671b5b53ed2920c1c5bbd70c828 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -123,7 +123,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
         * temporary wa and should be removed after fixing real cause
         * of forcewake timeouts.
         */
-       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
+       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
                pg_enable =
                        GEN9_MEDIA_PG_ENABLE |
                        GEN11_MEDIA_SAMPLER_PG_ENABLE;

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7a90a2e32c9f1bb41a159aaa8e00b3a50475f593..1fde21d8bb59a9cfb4e7a73dc22718566d3bc15e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -144,7 +144,7 @@ static const char *i915_cache_level_str(struct drm_i915_gem_object *obj)
 {
        struct drm_i915_private *i915 = obj_to_i915(obj);
 
-       if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) {
+       if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 74))) {
                switch (obj->pat_index) {
                case 0: return " WB";
                case 1: return " WT";