constraints.md (Cm2): New constraint for int -2.

	* config/avr/constraints.md (Cm2): New constraint for int -2.
	* config/avr/avr.md (addqi3): Use it. New alternatives for +/-2.
	(*negqihi2): New insn.

From-SVN: r181103

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4c7bdd5e93bfe4f3c230e39c72718a87047c5f58..cea9a6cb0670fec4f5b84f38957d7e2f7f7970b7 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2011-11-07  Georg-Johann Lay  <avr@gjlay.de>
+
+       * config/avr/constraints.md (Cm2): New constraint for int -2.
+       * config/avr/avr.md (addqi3): Use it. New alternatives for +/-2.
+       (*negqihi2): New insn.
+
 2011-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 
        * dwarf2cfi.c (dwarf2out_frame_debug_expr): Check

diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 12e94850c954e7fa61ef4a21fcc260424066782a..59330104fa00c06683b149ab5cfd81e4bbff2bf7 100644 (file)
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -752,17 +752,19 @@
 ; add bytes
 
 (define_insn "addqi3"
-  [(set (match_operand:QI 0 "register_operand" "=r,d,r,r")
-        (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0,0")
-                 (match_operand:QI 2 "nonmemory_operand" "r,i,P,N")))]
+  [(set (match_operand:QI 0 "register_operand"          "=r,d,r,r,r,r")
+        (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0")
+                 (match_operand:QI 2 "nonmemory_operand" "r,i,P,N,K,Cm2")))]
   ""
   "@
        add %0,%2
        subi %0,lo8(-(%2))
        inc %0
-       dec %0"
-  [(set_attr "length" "1,1,1,1")
-   (set_attr "cc" "set_czn,set_czn,set_zn,set_zn")])
+       dec %0
+       inc %0\;inc %0
+       dec %0\;dec %0"
+  [(set_attr "length" "1,1,1,1,2,2")
+   (set_attr "cc" "set_czn,set_czn,set_zn,set_zn,set_zn,set_zn")])
 
 
 (define_expand "addhi3"
@@ -3386,6 +3388,14 @@
   [(set_attr "length" "1")
    (set_attr "cc" "set_zn")])
 
+(define_insn "*negqihi2"
+  [(set (match_operand:HI 0 "register_operand"                        "=r")
+        (neg:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "0"))))]
+  ""
+  "clr %B0\;neg %A0\;brge .+2\;com %B0"
+  [(set_attr "length" "4")
+   (set_attr "cc" "set_n")])
+
 (define_insn "neghi2"
   [(set (match_operand:HI 0 "register_operand"       "=!d,r,&r")
        (neg:HI (match_operand:HI 1 "register_operand" "0,0,r")))]

diff --git a/gcc/config/avr/constraints.md b/gcc/config/avr/constraints.md
index 0f6a03adbf1973e99bc7ab9bf0ce36086a7849e4..50aae32b01a4a0012968e996c4f48270971dddb9 100644 (file)
--- a/gcc/config/avr/constraints.md
+++ b/gcc/config/avr/constraints.md
@@ -103,6 +103,11 @@
   (and (match_code "mem")
        (match_test "extra_constraint_Q (op)")))
 
+(define_constraint "Cm2"
+  "Constant integer @minus{}2."
+  (and (match_code "const_int")
+       (match_test "ival == -2")))
+
 (define_constraint "C03"
   "Constant integer 3."
   (and (match_code "const_int")