#include <config.h>
#include <errno.h>
-#include <fsl_esdhc_imx.h>
#include <hang.h>
#include <init.h>
#include <log.h>
#include <spl.h>
#include <asm/arch/ddr.h>
-#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
-#include <asm/io.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/gpio.h>
-#include <asm/mach-imx/mxc_i2c.h>
#include <asm/sections.h>
-#include <linux/delay.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
ddr_init(dram_timing);
}
-#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
- .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
- .gp = IMX_GPIO_NR(5, 14),
- },
- .sda = {
- .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
- .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
- .gp = IMX_GPIO_NR(5, 15),
- },
-};
-
-#if CONFIG_IS_ENABLED(MMC)
-#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
-#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
-#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-
- switch (cfg->esdhc_base) {
- case USDHC1_BASE_ADDR:
- /* the eMMC does not have a CD pin */
- return 1;
- case USDHC2_BASE_ADDR:
- return !gpio_get_value(USDHC2_CD_GPIO);
- }
-
- return 0;
-}
-
-#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
- PAD_CTL_FSEL2)
-#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
-
-static iomux_v3_cfg_t const usdhc1_pads[] = {
- IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
- IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
- IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
- IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
- IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
- IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
- IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
- IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
-};
-
-static struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC1_BASE_ADDR, 0, 8},
- {USDHC2_BASE_ADDR, 0, 4},
-};
-
-int board_mmc_init(struct bd_info *bis)
-{
- int i, ret;
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-Boot device node) (Physical Port)
- * mmc0 USDHC1
- * mmc1 USDHC2
- */
- for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- init_clk_usdhc(0);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
- imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
- ARRAY_SIZE(usdhc1_pads));
- gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
- gpio_direction_output(USDHC1_PWR_GPIO, 0);
- udelay(500);
- gpio_direction_output(USDHC1_PWR_GPIO, 1);
- break;
- case 1:
- init_clk_usdhc(1);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
- imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
- ARRAY_SIZE(usdhc2_pads));
- gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
- gpio_direction_output(USDHC2_PWR_GPIO, 0);
- udelay(500);
- gpio_direction_output(USDHC2_PWR_GPIO, 1);
- break;
- default:
- printf("Warning: you configured more USDHC controllers "
- "(%d) than supported by the board\n", i + 1);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
const char *spl_board_loader_name(u32 boot_device)
{
switch (boot_device) {
return NULL;
}
}
-#endif
-
-#if CONFIG_IS_ENABLED(POWER_LEGACY)
-#define I2C_PMIC 0
-static int pfuze_mode_init(struct pmic *p, u32 mode)
+static int pfuze_mode_init(struct udevice *dev, u32 mode)
{
unsigned char offset, i, switch_num;
u32 id;
int ret;
- pmic_reg_read(p, PFUZE100_DEVICEID, &id);
+ id = pmic_reg_read(dev, PFUZE100_DEVICEID);
id = id & 0xf;
if (id == 0) {
return -EINVAL;
}
- ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
+ ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);
if (ret < 0) {
printf("Set SW1AB mode error!\n");
return ret;
}
for (i = 0; i < switch_num - 1; i++) {
- ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
+ ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);
if (ret < 0) {
printf("Set switch 0x%x mode error!\n",
offset + i * SWITCH_SIZE);
int power_init_board(void)
{
- struct pmic *p;
+ struct udevice *dev;
+ int reg;
int ret;
- unsigned int reg;
- ret = power_pfuze100_init(I2C_PMIC);
- if (ret)
- return -ENODEV;
-
- p = pmic_get("PFUZE100");
- ret = pmic_probe(p);
- if (ret)
- return -ENODEV;
+ ret = pmic_get("pmic@8", &dev);
+ if (ret == -ENODEV) {
+ puts("No pmic@8\n");
+ return 0;
+ }
+ if (ret < 0)
+ return ret;
- pmic_reg_read(p, PFUZE100_SW3AVOL, ®);
+ reg = pmic_reg_read(dev, PFUZE100_SW3AVOL);
if ((reg & 0x3f) != 0x18) {
reg &= ~0x3f;
reg |= 0x18;
- pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
+ pmic_reg_write(dev, PFUZE100_SW3AVOL, reg);
}
- ret = pfuze_mode_init(p, APS_PFM);
+ ret = pfuze_mode_init(dev, APS_PFM);
if (ret < 0)
return ret;
/* set SW3A standby mode to off */
- pmic_reg_read(p, PFUZE100_SW3AMODE, ®);
+ reg = pmic_reg_read(dev, PFUZE100_SW3AMODE);
reg &= ~0xf;
reg |= APS_OFF;
- pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
+ pmic_reg_write(dev, PFUZE100_SW3AMODE, reg);
return 0;
}
-#endif
void board_init_f(ulong dummy)
{
int ret;
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
arch_cpu_init();
init_uart_clk(2);
timer_init();
- preloader_console_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- ret = spl_init();
+ ret = spl_early_init();
if (ret) {
- debug("spl_init() failed: %d\n", ret);
+ debug("spl_early_init() failed: %d\n", ret);
hang();
}
- enable_tzc380();
+ preloader_console_init();
- setup_i2c(0, 100000, 0x7f, &i2c_pad_info1);
+ enable_tzc380();
-#if CONFIG_IS_ENABLED(POWER_LEGACY)
power_init_board();
-#endif
spl_dram_init();
+ init_clk_usdhc(0);
+ init_clk_usdhc(1);
+
board_init_r(NULL, 0);
}
projects / thirdparty / u-boot.git / commitdiff
