clk: renesas: Add CPG/MSSR support to RZ/N2H SoC

Add clock driver support for the Renesas RZ/N2H (R9A09G087) SoC by reusing
the existing RZ/T2H (R9A09G077) CPG/MSSR implementation, as both SoCs
share the same clock and reset architecture.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250617155757.149597-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 45f9ae5b6ef1a59389061e9d114bde923a873673..6a5a046649906920f3d771d548814c2cd7af84ce 100644 (file)
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -44,6 +44,7 @@ config CLK_RENESAS
        select CLK_R9A09G056 if ARCH_R9A09G056
        select CLK_R9A09G057 if ARCH_R9A09G057
        select CLK_R9A09G077 if ARCH_R9A09G077
+       select CLK_R9A09G087 if ARCH_R9A09G087
        select CLK_SH73A0 if ARCH_SH73A0
 
 if CLK_RENESAS
@@ -213,6 +214,10 @@ config CLK_R9A09G077
        bool "RZ/T2H clock support" if COMPILE_TEST
        select CLK_RENESAS_CPG_MSSR
 
+config CLK_R9A09G087
+       bool "RZ/N2H clock support" if COMPILE_TEST
+       select CLK_RENESAS_CPG_MSSR
+
 config CLK_SH73A0
        bool "SH-Mobile AG5 clock support" if COMPILE_TEST
        select CLK_RENESAS_CPG_MSTP

diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index d8d894a15d24b83aa85f36d95f683cd487fb7059..d28eb276a1534137122a966c991b075ed1fa87eb 100644 (file)
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_CLK_R9A09G047)           += r9a09g047-cpg.o
 obj-$(CONFIG_CLK_R9A09G056)            += r9a09g056-cpg.o
 obj-$(CONFIG_CLK_R9A09G057)            += r9a09g057-cpg.o
 obj-$(CONFIG_CLK_R9A09G077)            += r9a09g077-cpg.o
+obj-$(CONFIG_CLK_R9A09G087)            += r9a09g077-cpg.o
 obj-$(CONFIG_CLK_SH73A0)               += clk-sh73a0.o
 
 # Family

diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c
index b83ef933ae0fb2dc67552641d9e8aec025858775..baf917ff4bebb49b2e49dfde6be7355c12bdf455 100644 (file)
--- a/drivers/clk/renesas/r9a09g077-cpg.c
+++ b/drivers/clk/renesas/r9a09g077-cpg.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 
 #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
+#include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
 #include "renesas-cpg-mssr.h"
 
 #define RZT2H_REG_BLOCK_SHIFT  11

diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 4a5ac9eef9cc805ce1589d06dbbe1dd1bf7f0eea..5ff6ee1f7d4b7d0009769b75944883f6f6ef6aec 100644 (file)
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -941,6 +941,12 @@ static const struct of_device_id cpg_mssr_match[] = {
                .compatible = "renesas,r9a09g077-cpg-mssr",
                .data = &r9a09g077_cpg_mssr_info,
        },
+#endif
+#ifdef CONFIG_CLK_R9A09G087
+       {
+               .compatible = "renesas,r9a09g087-cpg-mssr",
+               .data = &r9a09g077_cpg_mssr_info,
+       },
 #endif
        { /* sentinel */ }
 };