drm/amdgpu/vcn: Allow limiting ctx to instance 0 for AV1 at any time

commit 3318f2d20ce48849855df5e190813826d0bc3653 upstream.

There is no reason to require this to happen on first submitted IB only.
We need to wait for the queue to be idle, but it can be done at any
time (including when there are multiple video sessions active).

Signed-off-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 8908fdce0634a623404e9923ed2f536101a39db5)
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 9fb0d53805892df3e46470868f46e5cf5266ae3e..614e088655627170801841edb0a21274d8cad804 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -1875,15 +1875,19 @@ static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p,
                                struct amdgpu_job *job)
 {
        struct drm_gpu_scheduler **scheds;
-
-       /* The create msg must be in the first IB submitted */
-       if (atomic_read(&job->base.entity->fence_seq))
-               return -EINVAL;
+       struct dma_fence *fence;
 
        /* if VCN0 is harvested, we can't support AV1 */
        if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)
                return -EINVAL;
 
+       /* wait for all jobs to finish before switching to instance 0 */
+       fence = amdgpu_ctx_get_fence(p->ctx, job->base.entity, ~0ull);
+       if (fence) {
+               dma_fence_wait(fence, false);
+               dma_fence_put(fence);
+       }
+
        scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC]
                [AMDGPU_RING_PRIO_DEFAULT].sched;
        drm_sched_entity_modify_sched(job->base.entity, scheds, 1);

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 46c329a1b2f5f070dcb34a57726b88596ed49277..ec11484d3597c56eda925e6a2ae8ee068400bf2b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -1807,15 +1807,19 @@ static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p,
                                struct amdgpu_job *job)
 {
        struct drm_gpu_scheduler **scheds;
-
-       /* The create msg must be in the first IB submitted */
-       if (atomic_read(&job->base.entity->fence_seq))
-               return -EINVAL;
+       struct dma_fence *fence;
 
        /* if VCN0 is harvested, we can't support AV1 */
        if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)
                return -EINVAL;
 
+       /* wait for all jobs to finish before switching to instance 0 */
+       fence = amdgpu_ctx_get_fence(p->ctx, job->base.entity, ~0ull);
+       if (fence) {
+               dma_fence_wait(fence, false);
+               dma_fence_put(fence);
+       }
+
        scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC]
                [AMDGPU_RING_PRIO_0].sched;
        drm_sched_entity_modify_sched(job->base.entity, scheds, 1);