#define G3S_SEL_SDHI1 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 4, 2)
#define G3S_SEL_SDHI2 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 8, 2)
-#define DEF_G3S_MUX(_name, _id, _conf, _parent_names, _mux_flags, _clk_flags) \
- DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = (_conf), \
- .parent_names = (_parent_names), \
- .num_parents = ARRAY_SIZE((_parent_names)), \
- .mux_flags = CLK_MUX_HIWORD_MASK | (_mux_flags), \
- .flag = (_clk_flags))
-
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R9A08G045_SWD,