return &chan->vchan.chan.dev->device;
}
+static struct device *ddata2dev(struct stm32_dma3_ddata *ddata)
+{
+ return ddata->dma_dev.dev;
+}
+
static void stm32_dma3_chan_dump_reg(struct stm32_dma3_chan *chan)
{
struct stm32_dma3_ddata *ddata = to_stm32_dma3_ddata(chan);
struct stm32_dma3_ddata *ddata = to_stm32_dma3_ddata(chan);
int ret;
- ret = pm_runtime_resume_and_get(ddata->dma_dev.dev);
+ ret = pm_runtime_resume_and_get(ddata2dev(ddata));
if (ret < 0)
return ret;
chan->lli_pool = NULL;
err_put_sync:
- pm_runtime_put_sync(ddata->dma_dev.dev);
+ pm_runtime_put_sync(ddata2dev(ddata));
return ret;
}
if (chan->semaphore_mode)
stm32_dma3_put_chan_sem(chan);
- pm_runtime_put_sync(ddata->dma_dev.dev);
+ pm_runtime_put_sync(ddata2dev(ddata));
/* Reset configuration */
memset(&chan->dt_config, 0, sizeof(chan->dt_config));
if (!(mask & BIT(chan->id)))
return false;
- ret = pm_runtime_resume_and_get(ddata->dma_dev.dev);
+ ret = pm_runtime_resume_and_get(ddata2dev(ddata));
if (ret < 0)
return false;
semcr = readl_relaxed(ddata->base + STM32_DMA3_CSEMCR(chan->id));
- pm_runtime_put_sync(ddata->dma_dev.dev);
+ pm_runtime_put_sync(ddata2dev(ddata));
/* Check if chan is free */
if (semcr & CSEMCR_SEM_MUTEX)
struct dma_chan *c;
if (dma_spec->args_count < 3) {
- dev_err(ddata->dma_dev.dev, "Invalid args count\n");
+ dev_err(ddata2dev(ddata), "Invalid args count\n");
return NULL;
}
conf.tr_conf = dma_spec->args[2];
if (conf.req_line >= ddata->dma_requests) {
- dev_err(ddata->dma_dev.dev, "Invalid request line\n");
+ dev_err(ddata2dev(ddata), "Invalid request line\n");
return NULL;
}
/* Request dma channel among the generic dma controller list */
c = dma_request_channel(mask, stm32_dma3_filter_fn, &conf);
if (!c) {
- dev_err(ddata->dma_dev.dev, "No suitable channel found\n");
+ dev_err(ddata2dev(ddata), "No suitable channel found\n");
return NULL;
}
static u32 stm32_dma3_check_rif(struct stm32_dma3_ddata *ddata)
{
+ struct device *dev = ddata2dev(ddata);
u32 chan_reserved, mask = 0, i, ccidcfgr, invalid_cid = 0;
/* Reserve Secure channels */
* In case CID filtering is not configured, dma-channel-mask property can be used to
* specify available DMA channels to the kernel.
*/
- of_property_read_u32(ddata->dma_dev.dev->of_node, "dma-channel-mask", &mask);
+ of_property_read_u32(dev->of_node, "dma-channel-mask", &mask);
/* Reserve !CID-filtered not in dma-channel-mask, static CID != CID1, CID1 not allowed */
for (i = 0; i < ddata->dma_channels; i++) {
ddata->chans[i].semaphore_mode = true;
}
}
- dev_dbg(ddata->dma_dev.dev, "chan%d: %s mode, %s\n", i,
+ dev_dbg(dev, "chan%d: %s mode, %s\n", i,
!(ccidcfgr & CCIDCFGR_CFEN) ? "!CID-filtered" :
ddata->chans[i].semaphore_mode ? "Semaphore" : "Static CID",
(chan_reserved & BIT(i)) ? "denied" :
}
if (invalid_cid)
- dev_warn(ddata->dma_dev.dev, "chan%*pbl have invalid CID configuration\n",
+ dev_warn(dev, "chan%*pbl have invalid CID configuration\n",
ddata->dma_channels, &invalid_cid);
return chan_reserved;